diff options
19 files changed, 21 insertions, 19 deletions
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 8409c02..9f52bb5 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1562,7 +1562,9 @@ riscv_parse_add_subset (riscv_parse_subset_t *rps, rps->error_handler (_("x ISA extension `%s' must be set with the versions"), subset); - else + /* Allow old ISA spec can recognize zicsr and zifencei. */ + else if (strcmp (subset, "zicsr") != 0 + && strcmp (subset, "zifencei") != 0) rps->error_handler (_("cannot find default versions of the ISA extension `%s'"), subset); diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 5f8e118..1eed63c 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -104,7 +104,7 @@ struct riscv_csr_extra /* Need to sync the version with RISC-V compiler. */ #ifndef DEFAULT_RISCV_ISA_SPEC -#define DEFAULT_RISCV_ISA_SPEC "2.2" +#define DEFAULT_RISCV_ISA_SPEC "20191213" #endif #ifndef DEFAULT_RISCV_PRIV_SPEC diff --git a/gas/testsuite/gas/riscv/csr-version-1p10.d b/gas/testsuite/gas/riscv/csr-version-1p10.d index ee56ae3..88da724 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p10.d +++ b/gas/testsuite/gas/riscv/csr-version-1p10.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.10 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.10 #source: csr.s #warning_output: csr-version-1p10.l #objdump: -dr -Mpriv-spec=1.10 diff --git a/gas/testsuite/gas/riscv/csr-version-1p11.d b/gas/testsuite/gas/riscv/csr-version-1p11.d index a1d8169..b40c1d5 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p11.d +++ b/gas/testsuite/gas/riscv/csr-version-1p11.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.11 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.11 #source: csr.s #warning_output: csr-version-1p11.l #objdump: -dr -Mpriv-spec=1.11 diff --git a/gas/testsuite/gas/riscv/csr-version-1p12.d b/gas/testsuite/gas/riscv/csr-version-1p12.d index c4c2118..fbc30ee 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p12.d +++ b/gas/testsuite/gas/riscv/csr-version-1p12.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.12 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.12 #source: csr.s #warning_output: csr-version-1p12.l #objdump: -dr -Mpriv-spec=1.12 diff --git a/gas/testsuite/gas/riscv/csr-version-1p9p1.d b/gas/testsuite/gas/riscv/csr-version-1p9p1.d index 01e05ae..a96e8c9 100644 --- a/gas/testsuite/gas/riscv/csr-version-1p9p1.d +++ b/gas/testsuite/gas/riscv/csr-version-1p9p1.d @@ -1,4 +1,4 @@ -#as: -march=rv64i -mcsr-check -mpriv-spec=1.9.1 +#as: -march=rv64i_zicsr -mcsr-check -mpriv-spec=1.9.1 #source: csr.s #warning_output: csr-version-1p9p1.l #objdump: -dr -Mpriv-spec=1.9.1 diff --git a/gas/testsuite/gas/riscv/option-arch-03.d b/gas/testsuite/gas/riscv/option-arch-03.d index b621d03..62d7f7d 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.d +++ b/gas/testsuite/gas/riscv/option-arch-03.d @@ -4,5 +4,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_c2p0" + Tag_RISCV_arch: "rv32i2p1_c2p0" #... diff --git a/gas/testsuite/gas/riscv/option-arch-03.s b/gas/testsuite/gas/riscv/option-arch-03.s index d982a0b..ccdb1c3 100644 --- a/gas/testsuite/gas/riscv/option-arch-03.s +++ b/gas/testsuite/gas/riscv/option-arch-03.s @@ -1,3 +1,3 @@ .attribute arch, "rv64ic" .option arch, +d2p0, -c -.option arch, rv32ic +.option arch, rv32i2p1c2p0 diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d index c148cdb..a4b0322 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d index bc0e0fd..852fd55 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s index acc98a5..ea097f9 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0" + .attribute arch, "rv32i2p1_m2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s index 65d0fef..610c7e5 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0" + .attribute arch, "rv32i2p1" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d index 374a043..c1cf808 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d @@ -6,4 +6,4 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0" + Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s index b86cc55..3a9fb97 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_m2p0_xfoo2p0" + .attribute arch, "rv32i2p1_m2p0_xfoo2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s index 376e373..878f2de 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s @@ -1 +1 @@ - .attribute arch, "rv32i2p0_xbar2p0" + .attribute arch, "rv32i2p1_xbar2p0" diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d index 3f4935d..2f2638a 100644 --- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d +++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d @@ -23,5 +23,5 @@ Attribute Section: riscv File Attributes - Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0" + Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_zifencei2p0_xunknown4p0" #.. diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d index c6022be..f8f0229 100644 --- a/ld/testsuite/ld-riscv-elf/call-relax.d +++ b/ld/testsuite/ld-riscv-elf/call-relax.d @@ -3,7 +3,7 @@ #source: call-relax-1.s #source: call-relax-2.s #source: call-relax-3.s -#as: -march=rv32ic -mno-arch-attr +#as: -march=rv32ic_zicsr -mno-arch-attr #ld: -m[riscv_choose_ilp32_emul] #objdump: -d #pass |