diff options
author | Michael J. Eager <eager@eagercon.com> | 2023-10-07 15:29:54 -0700 |
---|---|---|
committer | Michael J. Eager <eager@eagercon.com> | 2023-10-07 15:33:10 -0700 |
commit | a3f612448356c1464b6b80265abf36b807c88b5d (patch) | |
tree | f77fb19fed6ffd59986b3ef93e1fc8691b64a184 /opcodes | |
parent | 6542e3df20652b96851c9f801ce199e3072792cf (diff) | |
download | binutils-a3f612448356c1464b6b80265abf36b807c88b5d.zip binutils-a3f612448356c1464b6b80265abf36b807c88b5d.tar.gz binutils-a3f612448356c1464b6b80265abf36b807c88b5d.tar.bz2 |
Revert "opcodes: microblaze: Add new bit-field instructions"
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9.
Maciej W. Rozycki <macro@orcam.me.uk>:
Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
microblaze-elf +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions:
microblaze-elf +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf +FAIL: binutils-all/pr26548
microblaze-elf +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
...
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/microblaze-dis.c | 16 | ||||
-rw-r--r-- | opcodes/microblaze-opc.h | 12 | ||||
-rw-r--r-- | opcodes/microblaze-opcm.h | 6 |
3 files changed, 2 insertions, 32 deletions
diff --git a/opcodes/microblaze-dis.c b/opcodes/microblaze-dis.c index d9db307..12981ab 100644 --- a/opcodes/microblaze-dis.c +++ b/opcodes/microblaze-dis.c @@ -91,18 +91,6 @@ get_field_imm5_mbar (struct string_buf *buf, long instr) } static char * -get_field_imm5width (struct string_buf *buf, long instr) -{ - char *p = strbuf (buf); - - if (instr & 0x00004000) - sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW))); /* bsefi */ - else - sprintf (p, "%d", (short)(((instr & IMM5_WIDTH_MASK) >> IMM_WIDTH_LOW) - ((instr & IMM5_MASK) >> IMM_LOW) + 1)); /* bsifi */ - return p; -} - -static char * get_field_rfsl (struct string_buf *buf, long instr) { char *p = strbuf (buf); @@ -439,10 +427,6 @@ print_insn_microblaze (bfd_vma memaddr, struct disassemble_info * info) /* For mbar 16 or sleep insn. */ case INST_TYPE_NONE: break; - /* For bit field insns. */ - case INST_TYPE_RD_R1_IMM5_IMM5: - print_func (stream, "\t%s, %s, %s, %s", get_field_rd (&buf, inst),get_field_r1(&buf, inst),get_field_imm5width (&buf, inst), get_field_imm5 (&buf, inst)); - break; /* For tuqula instruction */ case INST_TYPE_RD: print_func (stream, "\t%s", get_field_rd (&buf, inst)); diff --git a/opcodes/microblaze-opc.h b/opcodes/microblaze-opc.h index 63eb564..7398e9e 100644 --- a/opcodes/microblaze-opc.h +++ b/opcodes/microblaze-opc.h @@ -59,9 +59,6 @@ /* For mbar. */ #define INST_TYPE_IMM5 20 -/* For bsefi and bsifi */ -#define INST_TYPE_RD_R1_IMM5_IMM5 21 - #define INST_TYPE_NONE 25 @@ -92,9 +89,7 @@ #define OPCODE_MASK_H124 0xFFFF07FF /* High 16, and low 11 bits. */ #define OPCODE_MASK_H1234 0xFFFFFFFF /* All 32 bits. */ #define OPCODE_MASK_H3 0xFC000600 /* High 6 bits and bits 21, 22. */ -#define OPCODE_MASK_H3B 0xFC00C600 /* High 6 bits and bits 16, 17, 21, 22. */ #define OPCODE_MASK_H32 0xFC00FC00 /* High 6 bits and bit 16-21. */ -#define OPCODE_MASK_H32B 0xFC00C000 /* High 6 bits and bit 16, 17. */ #define OPCODE_MASK_H34B 0xFC0000FF /* High 6 bits and low 8 bits. */ #define OPCODE_MASK_H35B 0xFC0004FF /* High 6 bits and low 9 bits. */ #define OPCODE_MASK_H34C 0xFC0007E0 /* High 6 bits and bits 21-26. */ @@ -107,7 +102,7 @@ #define DELAY_SLOT 1 #define NO_DELAY_SLOT 0 -#define MAX_OPCODES 301 +#define MAX_OPCODES 300 const struct op_code_struct { @@ -164,8 +159,6 @@ const struct op_code_struct {"bslli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000400, OPCODE_MASK_H3, bslli, barrel_shift_inst }, {"bsrai", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000200, OPCODE_MASK_H3, bsrai, barrel_shift_inst }, {"bsrli", INST_TYPE_RD_R1_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64000000, OPCODE_MASK_H3, bsrli, barrel_shift_inst }, - {"bsefi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64004000, OPCODE_MASK_H32B, bsefi, barrel_shift_inst }, - {"bsifi", INST_TYPE_RD_R1_IMM5_IMM5, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x64008000, OPCODE_MASK_H32B, bsifi, barrel_shift_inst }, {"or", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x80000000, OPCODE_MASK_H4, microblaze_or, logical_inst }, {"and", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x84000000, OPCODE_MASK_H4, microblaze_and, logical_inst }, {"xor", INST_TYPE_RD_R1_R2, INST_NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0x88000000, OPCODE_MASK_H4, microblaze_xor, logical_inst }, @@ -445,8 +438,5 @@ char pvr_register_prefix[] = "rpvr"; #define MIN_IMM5 ((int) 0x00000000) #define MAX_IMM5 ((int) 0x0000001f) -#define MIN_IMM_WIDTH ((int) 0x00000001) -#define MAX_IMM_WIDTH ((int) 0x00000020) - #endif /* MICROBLAZE_OPC */ diff --git a/opcodes/microblaze-opcm.h b/opcodes/microblaze-opcm.h index 3c4f894..c91b002 100644 --- a/opcodes/microblaze-opcm.h +++ b/opcodes/microblaze-opcm.h @@ -29,7 +29,7 @@ enum microblaze_instr addi, rsubi, addic, rsubic, addik, rsubik, addikc, rsubikc, mul, mulh, mulhu, mulhsu, swapb, swaph, idiv, idivu, bsll, bsra, bsrl, get, put, nget, nput, cget, cput, - ncget, ncput, muli, bslli, bsrai, bsrli, bsefi, bsifi, mului, + ncget, ncput, muli, bslli, bsrai, bsrli, mului, /* 'or/and/xor' are C++ keywords. */ microblaze_or, microblaze_and, microblaze_xor, andn, pcmpbf, pcmpbc, pcmpeq, pcmpne, sra, src, srl, sext8, sext16, @@ -130,7 +130,6 @@ enum microblaze_instr_type #define RB_LOW 11 /* Low bit for RB. */ #define IMM_LOW 0 /* Low bit for immediate. */ #define IMM_MBAR 21 /* low bit for mbar instruction. */ -#define IMM_WIDTH_LOW 6 /* Low bit for immediate width */ #define RD_MASK 0x03E00000 #define RA_MASK 0x001F0000 @@ -143,9 +142,6 @@ enum microblaze_instr_type /* Imm mask for mbar. */ #define IMM5_MBAR_MASK 0x03E00000 -/* Imm mask for extract/insert width. */ -#define IMM5_WIDTH_MASK 0x000007C0 - /* FSL imm mask for get, put instructions. */ #define RFSL_MASK 0x000000F |