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author | Jan Beulich <jbeulich@suse.com> | 2023-08-07 11:56:50 +0200 |
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committer | Jan Beulich <jbeulich@suse.com> | 2023-08-07 11:56:50 +0200 |
commit | 8d27b09d0877982dc2252c01a3f1d9c631b2d6eb (patch) | |
tree | 752ee08beb1b001d35a84ca089f85675ce184ee1 /opcodes | |
parent | 2f98b09492b33b95afcc1ac22d212ee4a5be0149 (diff) | |
download | binutils-8d27b09d0877982dc2252c01a3f1d9c631b2d6eb.zip binutils-8d27b09d0877982dc2252c01a3f1d9c631b2d6eb.tar.gz binutils-8d27b09d0877982dc2252c01a3f1d9c631b2d6eb.tar.bz2 |
RISC-V: move comment describing rules for riscv_opcodes[]
It makes little sense to have this comment meanwhile over a hundred
lines ahead of the array. In fact until spotting the comment, I was
wondering why those pretty important aspects aren't spelled out
anywhere.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/riscv-opc.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 6a85473..3efab9a 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -131,16 +131,6 @@ const float riscv_fli_numval[32] = 0x1p+3, 0x1p+4, 0x1p+7, 0x1p+8, 0x1p+15, 0x1p+16, 0x0p+0, 0x0p+0 }; -/* The order of overloaded instructions matters. Label arguments and - register arguments look the same. Instructions that can have either - for arguments must apear in the correct order in this table for the - assembler to pick the right one. In other words, entries with - immediate operands must apear after the same instruction with - registers. - - Because of the lookup algorithm used, entries with the same opcode - name must be contiguous. */ - #define MASK_RS1 (OP_MASK_RS1 << OP_SH_RS1) #define MASK_RS2 (OP_MASK_RS2 << OP_SH_RS2) #define MASK_RD (OP_MASK_RD << OP_SH_RD) @@ -329,6 +319,16 @@ match_th_load_pair(const struct riscv_opcode *op, return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); } +/* The order of overloaded instructions matters. Label arguments and + register arguments look the same. Instructions that can have either + for arguments must apear in the correct order in this table for the + assembler to pick the right one. In other words, entries with + immediate operands must apear after the same instruction with + registers. + + Because of the lookup algorithm used, entries with the same opcode + name must be contiguous. */ + const struct riscv_opcode riscv_opcodes[] = { /* name, xlen, isa, operands, match, mask, match_func, pinfo. */ |