MIPS/opcodes: Reorder coprocessor moves alphabetically

A number of coprocessor move encodings have been randomly sprinkled over
the regular MIPS and microMIPS opcode tables rather than where they'd be
expected following the alphabetic order.  Fix the ordering, taking into
account precedence where it has to be observed for correct disassembly.
No functional change.

1 files changed, 52 insertions, 48 deletions

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index aff544d..a89747b 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -1105,20 +1105,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmadd16",		"s,t",		0x00000029, 0xfc00ffff, RD_1|RD_2|MOD_LO,       0,		N411,		0,	0 },
 {"dmfc0",		"t,G",		0x40200000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		I3,		0,	EE },
 {"dmfc0",		"t,G,H",	0x40200000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		I64,		0,	0 },
+{"dmfc1",		"t,S",		0x44200000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I3,		0,	SF },
+{"dmfc1",		"t,G",		0x44200000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I3,		0,	SF },
+/* dmfc2 is at the bottom of the table.  */
 {"dmfgc0",		"t,G",		0x40600100, 0xffe007ff, WR_1|RD_C0|LC,		0,		0,		IVIRT64, 0 },
 {"dmfgc0",		"t,G,H",	0x40600100, 0xffe007f8, WR_1|RD_C0|LC,		0,		0,		IVIRT64, 0 },
 {"dmt",			"",		0x41600bc1, 0xffffffff, TRAP,			0,		0,		MT32,	0 },
 {"dmt",			"t",		0x41600bc1, 0xffe0ffff, WR_1|TRAP,		0,		0,		MT32,	0 },
 {"dmtc0",		"t,G",		0x40a00000, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		I3,		0,	EE },
 {"dmtc0",		"t,G,H",	0x40a00000, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		I64,		0,	0 },
-{"dmtgc0",		"t,G",		0x40600300, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,	0,		0,		IVIRT64, 0 },
-{"dmtgc0",		"t,G,H",	0x40600300, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,		0,		IVIRT64, 0 },
-{"dmfc1",		"t,S",		0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,	0,		I3,		0,	SF },
-{"dmfc1",		"t,G",		0x44200000, 0xffe007ff, WR_1|RD_2|LC|FP_D,     0,		I3,		0,	SF },
 {"dmtc1",		"t,S",		0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,	0,		I3,		0,	SF },
 {"dmtc1",		"t,G",		0x44a00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,     0,		I3,		0,	SF },
-/* dmfc2 is at the bottom of the table.  */
 /* dmtc2 is at the bottom of the table.  */
+{"dmtgc0",		"t,G",		0x40600300, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		0,		IVIRT64, 0 },
+{"dmtgc0",		"t,G,H",	0x40600300, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		0,		IVIRT64, 0 },
 {"dmuh",		"d,s,t",	0x000000dc, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,s,t",	0x0000009c, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		I69,		0,	0 },
 {"dmul",		"d,v,t",	0x70000003, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,	0,		IOCT,		0,	0 },
@@ -1397,14 +1397,41 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"max.s",		"D,S,T",	0x46000028, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,	0,		EE,		0,	0 },
 {"max.s",		"D,S,T",	0x4600001e, 0xffe0003f,	WR_1|RD_2|RD_3|FP_S,	0,		I37,		0,	0 },
 {"mfbpc",		"t",		0x4000c000, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
+/* mfps overlaps with mfc0, so it's here to take precedence.  */
+{"mfps",		"t,P",		0x4000c800, 0xffe0ffc1,	WR_1|RD_C0|LC,		0,		M1|N5|EE,	0,	0 },
+{"mfc0",		"t,G",		0x40000000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		I1,		0,	0 },
+{"mfc0",		"t,G,H",	0x40000000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		I32,		0,	0 },
+{"mfc1",		"t,S",		0x44000000, 0xffe007ff,	WR_1|RD_2|LC|FP_S,	0,		I1,		0,	0 },
+{"mfc1",		"t,G",		0x44000000, 0xffe007ff,	WR_1|RD_2|LC|FP_S,	0,		I1,		0,	0 },
+/* mfc2 is at the bottom of the table.  */
+/* mfc3 is at the bottom of the table.  */
+{"mfcr",		"t,s",		0x70000018, 0xfc00ffff,	WR_1|RD_2,		0,		XLR,		0,	0 },
 {"mfdab",		"t",		0x4000c004, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
 {"mfdabm",		"t",		0x4000c005, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
+{"mfdr",		"t,G",		0x7000003d, 0xffe007ff,	WR_1|RD_C0|LC,		0,		N5|ALX,		0,	0 },
 {"mfdvb",		"t",		0x4000c006, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
 {"mfdvbm",		"t",		0x4000c007, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
+{"mfgc0",		"t,G",		0x40600000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		IVIRT,	0 },
+{"mfgc0",		"t,G,H",	0x40600000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		0,		IVIRT,	0 },
+{"mfhc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		XPA,	0 },
+{"mfhc0",		"t,G,H",	0x40400000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		0,		XPA,	0 },
+{"mfhc1",		"t,S",		0x44600000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I33,		0,	0 },
+{"mfhc1",		"t,G",		0x44600000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I33,		0,	0 },
+/* mfhc2 is at the bottom of the table.  */
+{"mfhgc0",		"t,G",		0x40600400, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		XPAVZ,	0 },
+{"mfhgc0",		"t,G,H",	0x40600400, 0xffe007f8,	WR_1|RD_C0|LC,		0,		0,		XPAVZ,	0 },
+{"mfhi",		"d",		0x00000010, 0xffff07ff,	WR_1|RD_HI,		0,		I1,		0,	I37 },
+{"mfhi",		"d,9",		0x00000010, 0xff9f07ff,	WR_1|RD_HI,		0,		0,		D32,	0 },
+{"mfhi1",		"d",		0x70000010, 0xffff07ff,	WR_1|RD_HI,		0,		EE,		0,	0 },
 {"mfiab",		"t",		0x4000c002, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
 {"mfiabm",		"t",		0x4000c003, 0xffe0ffff,	WR_1|RD_C0|LC,		0,		EE,		0,	0 },
+{"mflo",		"d",		0x00000012, 0xffff07ff,	WR_1|RD_LO,		0,		I1,		0,	I37 },
+{"mflo",		"d,9",		0x00000012, 0xff9f07ff,	WR_1|RD_LO,		0,		0,		D32,	0 },
+{"mflo1",		"d",		0x70000012, 0xffff07ff,	WR_1|RD_LO,		0,		EE,		0,	0 },
+{"mflhxu",		"d",		0x00000052, 0xffff07ff,	WR_1|MOD_HILO,		0,		0,		SMT,	0 },
 {"mfpc",		"t,P",		0x4000c801, 0xffe0ffc1,	WR_1|RD_C0|LC,		0,		M1|N5|EE,	0,	0 },
-{"mfps",		"t,P",		0x4000c800, 0xffe0ffc1,	WR_1|RD_C0|LC,		0,		M1|N5|EE,	0,	0 },
+/* mfps is above mfc0.  */
+{"mfsa",		"d",		0x00000028, 0xffff07ff,	WR_1,			0,		EE,		0,	0 },
 {"mftacx",		"d",		0x41020021, 0xffff07ff, WR_1|RD_a|TRAP,		0,		0,		MT32,	0 },
 {"mftacx",		"d,*",		0x41020021, 0xfff307ff, WR_1|RD_a|TRAP,		0,		0,		MT32,	0 },
 {"mftc0",		"d,E",		0x41000000, 0xffe007ff, WR_1|RD_C0|TRAP|LC,	0,		0,		MT32,	0 },
@@ -1422,31 +1449,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mftlo",		"d",		0x41000021, 0xffff07ff, WR_1|RD_a|TRAP,		0,		0,		MT32,	0 },
 {"mftlo",		"d,*",		0x41000021, 0xfff307ff, WR_1|RD_a|TRAP,		0,		0,		MT32,	0 },
 {"mftr",		"d,E,!,H,$",	0x41000000, 0xffe007c8, WR_1|TRAP,		0,		0,		MT32,	0 },
-{"mfc0",		"t,G",		0x40000000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		I1,		0,	0 },
-{"mfc0",		"t,G,H",	0x40000000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		I32,		0,	0 },
-{"mfgc0",		"t,G",		0x40600000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		IVIRT,	0 },
-{"mfgc0",		"t,G,H",	0x40600000, 0xffe007f8, WR_1|RD_C0|LC,		0,		0,		IVIRT,	0 },
-{"mfhc0",		"t,G",		0x40400000, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		XPA,	0 },
-{"mfhc0",		"t,G,H",	0x40400000, 0xffe007f8,	WR_1|RD_C0|LC,		0,		0,		XPA,	0 },
-{"mfhgc0",		"t,G",		0x40600400, 0xffe007ff,	WR_1|RD_C0|LC,		0,		0,		XPAVZ,	0 },
-{"mfhgc0",		"t,G,H",	0x40600400, 0xffe007f8,	WR_1|RD_C0|LC,		0,		0,		XPAVZ,	0 },
-{"mfc1",		"t,S",		0x44000000, 0xffe007ff,	WR_1|RD_2|LC|FP_S,	0,		I1,		0,	0 },
-{"mfc1",		"t,G",		0x44000000, 0xffe007ff,	WR_1|RD_2|LC|FP_S,	0,		I1,		0,	0 },
-{"mfhc1",		"t,S",		0x44600000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I33,		0,	0 },
-{"mfhc1",		"t,G",		0x44600000, 0xffe007ff,	WR_1|RD_2|LC|FP_D,	0,		I33,		0,	0 },
-/* mfc2 is at the bottom of the table.  */
-/* mfhc2 is at the bottom of the table.  */
-/* mfc3 is at the bottom of the table.  */
-{"mfdr",		"t,G",		0x7000003d, 0xffe007ff,	WR_1|RD_C0|LC,		0,		N5|ALX,		0,	0 },
-{"mfhi",		"d",		0x00000010, 0xffff07ff,	WR_1|RD_HI,		0,		I1,		0,	I37 },
-{"mfhi",		"d,9",		0x00000010, 0xff9f07ff, WR_1|RD_HI,		0,		0,		D32,	0 },
-{"mfhi1",		"d",		0x70000010, 0xffff07ff,	WR_1|RD_HI,		0,		EE,		0,	0 },
-{"mflo",		"d",		0x00000012, 0xffff07ff,	WR_1|RD_LO,		0,		I1,		0,	I37 },
-{"mflo",		"d,9",		0x00000012, 0xff9f07ff, WR_1|RD_LO,		0,		0,		D32,	0 },
-{"mflo1",		"d",		0x70000012, 0xffff07ff,	WR_1|RD_LO,		0,		EE,		0,	0 },
-{"mflhxu",		"d",		0x00000052, 0xffff07ff,	WR_1|MOD_HILO,		0,		0,		SMT,	0 },
-{"mfcr",		"t,s",		0x70000018, 0xfc00ffff, WR_1|RD_2,		0,		XLR,		0,	0 },
-{"mfsa",		"d",		0x00000028, 0xffff07ff,	WR_1,			0,		EE,		0,	0 },
 {"min",			"d,v,t",	0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,		0,		ALX,		0,	0 },
 {"min.ob",		"X,Y,Q",	0x78000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		SB1,		MX,	0 },
 {"min.ob",		"D,S,Q",	0x48000006, 0xfc20003f,	WR_1|RD_2|RD_3|FP_D,	0,		N54,		0,	0 },
@@ -1515,38 +1517,38 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"msubu",		"s,t",		0x70000005, 0xfc00ffff, RD_1|RD_2|MOD_HILO,     0,		I32|N55,	0,	I37 },
 {"msubu",		"7,s,t",	0x70000005, 0xfc00e7ff, RD_2|RD_3|MOD_a,        0,              0,		D32,	0 },
 {"mtbpc",		"t",		0x4080c000, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
+/* mtps overlaps with mtc0, so it's here to take precedence.  */
+{"mtps",		"t,P",		0x4080c800, 0xffe0ffc1,	RD_1|WR_C0|CM,		0,		M1|N5|EE,	0,	0 },
+{"mtc0",		"t,G",		0x40800000, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		I1,		0,	0 },
+{"mtc0",		"t,G,H",	0x40800000, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		I32,		0,	0 },
+{"mtc1",		"t,S",		0x44800000, 0xffe007ff,	RD_1|WR_2|CM|FP_S,	0,		I1,		0,	0 },
+{"mtc1",		"t,G",		0x44800000, 0xffe007ff,	RD_1|WR_2|CM|FP_S,	0,		I1,		0,	0 },
+/* mtc2 is at the bottom of the table.  */
+/* mtc3 is at the bottom of the table.  */
+{"mtcr",		"t,s",		0x70000019, 0xfc00ffff,	RD_1|RD_2,		0,		XLR,		0,	0 },
 {"mtdab",		"t",		0x4080c004, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
 {"mtdabm",		"t",		0x4080c005, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
+{"mtdr",		"t,G",		0x7080003d, 0xffe007ff,	RD_1|WR_C0|CM,		0,		N5|ALX,		0,	0 },
 {"mtdvb",		"t",		0x4080c006, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
 {"mtdvbm",		"t",		0x4080c007, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
-{"mtiab",		"t",		0x4080c002, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
-{"mtiabm",		"t",		0x4080c003, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
-{"mtpc",		"t,P",		0x4080c801, 0xffe0ffc1,	RD_1|WR_C0|CM,		0,		M1|N5|EE,	0,	0 },
-{"mtps",		"t,P",		0x4080c800, 0xffe0ffc1,	RD_1|WR_C0|CM,		0,		M1|N5|EE,	0,	0 },
-{"mtc0",		"t,G",		0x40800000, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		I1,		0,	0 },
-{"mtc0",		"t,G,H",	0x40800000, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		I32,		0,	0 },
 {"mtgc0",		"t,G",		0x40600200, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		0,		IVIRT,	0 },
 {"mtgc0",		"t,G,H",	0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,		0,		IVIRT,	0 },
 {"mthc0",		"t,G",		0x40c00000, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPA,	0 },
 {"mthc0",		"t,G,H",	0x40c00000, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPA,	0 },
-{"mthgc0",		"t,G",		0x40600600, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPAVZ,	0 },
-{"mthgc0",		"t,G,H",	0x40600600, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPAVZ,	0 },
-{"mtc1",		"t,S",		0x44800000, 0xffe007ff,	RD_1|WR_2|CM|FP_S,	0,		I1,		0,	0 },
-{"mtc1",		"t,G",		0x44800000, 0xffe007ff,	RD_1|WR_2|CM|FP_S,	0,		I1,		0,	0 },
 {"mthc1",		"t,S",		0x44e00000, 0xffe007ff,	RD_1|WR_2|CM|FP_D,	0,		I33,		0,	0 },
 {"mthc1",		"t,G",		0x44e00000, 0xffe007ff,	RD_1|WR_2|CM|FP_D,	0,		I33,		0,	0 },
-/* mtc2 is at the bottom of the table.  */
 /* mthc2 is at the bottom of the table.  */
-/* mtc3 is at the bottom of the table.  */
-{"mtdr",		"t,G",		0x7080003d, 0xffe007ff,	RD_1|WR_C0|CM,		0,		N5|ALX,		0,	0 },
+{"mthgc0",		"t,G",		0x40600600, 0xffe007ff,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPAVZ,	0 },
+{"mthgc0",		"t,G,H",	0x40600600, 0xffe007f8,	RD_1|WR_C0|WR_CC|CM,	0,		0,		XPAVZ,	0 },
 {"mthi",		"s",		0x00000011, 0xfc1fffff,	RD_1|WR_HI,		0,		I1,		0,	I37 },
 {"mthi",		"s,7",		0x00000011, 0xfc1fe7ff, RD_1|WR_HI,		0,		0,		D32,	0 },
 {"mthi1",		"s",		0x70000011, 0xfc1fffff,	RD_1|WR_HI,		0,		EE,		0,	0 },
+{"mtiab",		"t",		0x4080c002, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
+{"mtiabm",		"t",		0x4080c003, 0xffe0ffff,	RD_1|WR_C0|CM,		0,		EE,		0,	0 },
+{"mtlhx",		"s",		0x00000053, 0xfc1fffff,	RD_1|MOD_HILO,		0,		0,		SMT,	0 },
 {"mtlo",		"s",		0x00000013, 0xfc1fffff,	RD_1|WR_LO,		0,		I1,		0,	I37 },
 {"mtlo",		"s,7",		0x00000013, 0xfc1fe7ff, RD_1|WR_LO,		0,		0,		D32,	0 },
 {"mtlo1",		"s",		0x70000013, 0xfc1fffff,	RD_1|WR_LO,		0,		EE,		0,	0 },
-{"mtlhx",		"s",		0x00000053, 0xfc1fffff,	RD_1|MOD_HILO,		0,		0,		SMT,	0 },
-{"mtcr",		"t,s",		0x70000019, 0xfc00ffff, RD_1|RD_2,		0,		XLR,		0,	0 },
 {"mtm0",		"s",		0x70000008, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
 {"mtm0",    		"s,t",		0x70000008, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtm1",		"s",		0x7000000c, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
@@ -1559,16 +1561,18 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtp1",    		"s,t",		0x7000000a, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
 {"mtp2",		"s",		0x7000000b, 0xfc1fffff, RD_1,			0,		IOCT,		0,	0 },
 {"mtp2",    		"s,t",		0x7000000b, 0xfc00ffff, RD_1|RD_2,		0,		IOCT3,		0,	0 },
+{"mtpc",		"t,P",		0x4080c801, 0xffe0ffc1,	RD_1|WR_C0|CM,		0,		M1|N5|EE,	0,	0 },
+/* mtps is above mtc0.  */
 {"mtsa",		"s",		0x00000029, 0xfc1fffff,	RD_1,			0,		EE,		0,	0 },
 {"mtsab",		"s,j",		0x04180000, 0xfc1f0000,	RD_1,			0,		EE,		0,	0 },
 {"mtsah",		"s,j",		0x04190000, 0xfc1f0000,	RD_1,			0,		EE,		0,	0 },
+{"mttacx",		"t",		0x41801021, 0xffe0ffff,	RD_1|WR_a|TRAP,		0,		0,		MT32,	0 },
+{"mttacx",		"t,&",		0x41801021, 0xffe09fff,	RD_1|WR_a|TRAP,		0,		0,		MT32,	0 },
 {"mttc0",		"t,G",		0x41800000, 0xffe007ff, RD_1|WR_C0|WR_CC|TRAP|CM, 0,		0,		MT32,	0 },
 {"mttc0",		"t,G,H",	0x41800000, 0xffe007f8, RD_1|WR_C0|WR_CC|TRAP|CM, 0,		0,		MT32,	0 },
 {"mttc1",		"t,S",		0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,		0,		MT32,	0 },
 {"mttc1",		"t,G",		0x41800022, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_S, 0,		0,		MT32,	0 },
 {"mttc2",		"t,G",		0x41800024, 0xffe007ff,	RD_1|WR_C2|WR_CC|TRAP|CM, 0,		0,		MT32,	IOCT|IOCTP|IOCT2 },
-{"mttacx",		"t",		0x41801021, 0xffe0ffff, RD_1|WR_a|TRAP,		0,		0,		MT32,	0 },
-{"mttacx",		"t,&",		0x41801021, 0xffe09fff, RD_1|WR_a|TRAP,		0,		0,		MT32,	0 },
 {"mttdsp",		"t",		0x41808021, 0xffe0ffff, RD_1|TRAP,		0,		0,		MT32,	0 },
 {"mttgpr",		"t,d",		0x41800020, 0xffe007ff, RD_1|WR_2|TRAP,		0,		0,		MT32,	0 },
 {"mtthc1",		"t,S",		0x41800032, 0xffe007ff, RD_1|WR_2|TRAP|CM|FP_D, 0,		0,		MT32,	0 },