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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:07:39 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:32:03 +0800 |
| commit | 1ba39b6fe595d05bbfdf7abebaea2883ddb9d717 (patch) | |
| tree | 3e13fc633f0cfe9df234e7167151f93781d88f95 /include | |
| parent | 9a51da2636778dce2e2635cb10822a92a51b2b9e (diff) | |
| download | binutils-1ba39b6fe595d05bbfdf7abebaea2883ddb9d717.zip binutils-1ba39b6fe595d05bbfdf7abebaea2883ddb9d717.tar.gz binutils-1ba39b6fe595d05bbfdf7abebaea2883ddb9d717.tar.bz2 | |
RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* testsuite/gas/riscv/x-thead-vector.d: Add tests for
floating-point arithmetic instructions.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 5cca4c5..2e5b4fe 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2909,6 +2909,42 @@ #define MASK_TH_VASUBVX 0xfc00707f #define MATCH_TH_VWSMACCSUVV 0xf8000057 #define MASK_TH_VWSMACCSUVV 0xfc00707f +#define MATCH_TH_VFSQRTV 0x8c001057 +#define MASK_TH_VFSQRTV 0xfc0ff07f +#define MATCH_TH_VMFORDVV 0x68001057 +#define MASK_TH_VMFORDVV 0xfc00707f +#define MATCH_TH_VMFORDVF 0x68005057 +#define MASK_TH_VMFORDVF 0xfc00707f +#define MATCH_TH_VFCLASSV 0x8c081057 +#define MASK_TH_VFCLASSV 0xfc0ff07f +#define MATCH_TH_VFCVTXUFV 0x88001057 +#define MASK_TH_VFCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFCVTXFV 0x88009057 +#define MASK_TH_VFCVTXFV 0xfc0ff07f +#define MATCH_TH_VFCVTFXUV 0x88011057 +#define MASK_TH_VFCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFCVTFXV 0x88019057 +#define MASK_TH_VFCVTFXV 0xfc0ff07f +#define MATCH_TH_VFWCVTXUFV 0x88041057 +#define MASK_TH_VFWCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFWCVTXFV 0x88049057 +#define MASK_TH_VFWCVTXFV 0xfc0ff07f +#define MATCH_TH_VFWCVTFXUV 0x88051057 +#define MASK_TH_VFWCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFWCVTFXV 0x88059057 +#define MASK_TH_VFWCVTFXV 0xfc0ff07f +#define MATCH_TH_VFWCVTFFV 0x88061057 +#define MASK_TH_VFWCVTFFV 0xfc0ff07f +#define MATCH_TH_VFNCVTXUFV 0x88081057 +#define MASK_TH_VFNCVTXUFV 0xfc0ff07f +#define MATCH_TH_VFNCVTXFV 0x88089057 +#define MASK_TH_VFNCVTXFV 0xfc0ff07f +#define MATCH_TH_VFNCVTFXUV 0x88091057 +#define MASK_TH_VFNCVTFXUV 0xfc0ff07f +#define MATCH_TH_VFNCVTFXV 0x88099057 +#define MASK_TH_VFNCVTFXV 0xfc0ff07f +#define MATCH_TH_VFNCVTFFV 0x880a1057 +#define MASK_TH_VFNCVTFFV 0xfc0ff07f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f |