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| author | Jim Wilson <jimw@sifive.com> | 2019-09-17 17:59:08 -0700 |
|---|---|---|
| committer | Jim Wilson <jimw@sifive.com> | 2019-09-17 17:59:08 -0700 |
| commit | 7e9ad3a35cde2342e07c34345d5ee671ea8aeeb4 (patch) | |
| tree | 5e7c5bf918a812bd4b385addf9fe10b616e10f9c /include | |
| parent | 491144b5e21bbfd41969c175aebb663976f59058 (diff) | |
| download | binutils-7e9ad3a35cde2342e07c34345d5ee671ea8aeeb4.zip binutils-7e9ad3a35cde2342e07c34345d5ee671ea8aeeb4.tar.gz binutils-7e9ad3a35cde2342e07c34345d5ee671ea8aeeb4.tar.bz2 | |
RISC-V: Gate opcode tables by enum rather than string.
Generalize opcode arch dependencies so that we can support the
overlapping B extension Zb* subsets.
2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
gas/
* config/tc-riscv.c (riscv_multi_subset_supports): Handle
insn_class enum rather than subset char string.
(riscv_ip): Update call to riscv_multi_subset_supports.
include/
* opcode/riscv.h (riscv_insn_class): New enum.
* opcode/riscv.h (struct riscv_opcode): Change
subset field to insn_class field.
opcodes/
* riscv-opc.c (riscv_opcodes): Change subset field
to insn_class field for all instructions.
(riscv_insn_types): Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 6 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 23 |
2 files changed, 26 insertions, 3 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index eb500e1..c725bfb 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,9 @@ +2019-09-17 Maxim Blinov <maxim.blinov@embecosm.com> + + * opcode/riscv.h (riscv_insn_class): New enum. + * opcode/riscv.h (struct riscv_opcode): Change + subset field to insn_class field. + 2019-09-09 Phil Blundell <pb@pbcl.net> binutils 2.33 branch created. diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 4acc25c..bfb96c8 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -294,6 +294,23 @@ static const char * const riscv_pred_succ[16] = /* The maximal number of subset can be required. */ #define MAX_SUBSET_NUM 4 +/* All RISC-V instructions belong to at least one of these classes. */ + +enum riscv_insn_class + { + INSN_CLASS_NONE, + + INSN_CLASS_I, + INSN_CLASS_C, + INSN_CLASS_A, + INSN_CLASS_M, + INSN_CLASS_F, + INSN_CLASS_D, + INSN_CLASS_D_AND_C, + INSN_CLASS_F_AND_C, + INSN_CLASS_Q, + }; + /* This structure holds information for a particular instruction. */ struct riscv_opcode @@ -302,9 +319,9 @@ struct riscv_opcode const char *name; /* The requirement of xlen for the instruction, 0 if no requirement. */ unsigned xlen_requirement; - /* An array of ISA subset name (I, M, A, F, D, Xextension), must ended - with a NULL pointer sential. */ - const char *subset[MAX_SUBSET_NUM]; + /* Class to which this instruction belongs. Used to decide whether or + not this instruction is legal in the current -march context. */ + enum riscv_insn_class insn_class; /* A string describing the arguments for this instruction. */ const char *args; /* The basic opcode for the instruction. When assembling, this |