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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2022-06-28 17:44:46 +0200 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@vrull.eu> | 2022-09-22 18:06:09 +0200 |
| commit | 4041e11db3ec3611921d10150572a92689aa3154 (patch) | |
| tree | bba8aafa39329d95a4cc101c5672a52689033b44 /include | |
| parent | 73442230966a22b3238b2074691a71d7b4ed914a (diff) | |
| download | binutils-4041e11db3ec3611921d10150572a92689aa3154.zip binutils-4041e11db3ec3611921d10150572a92689aa3154.tar.gz binutils-4041e11db3ec3611921d10150572a92689aa3154.tar.bz2 | |
RISC-V: Add T-Head MAC vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.
This patch adds the XTheadMac extension, a collection of
T-Head-specific multiply-accumulate instructions.
The 'th' prefix and the "XTheadMac" extension are documented
in a PR for the RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv-opc.h | 20 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 21 insertions, 0 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 5c0f610..b504ce0 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2186,6 +2186,19 @@ #define MASK_TH_MVEQZ 0xfe00707f #define MATCH_TH_MVNEZ 0x4200100b #define MASK_TH_MVNEZ 0xfe00707f +/* Vendor-specific (T-Head) XTheadMac instructions. */ +#define MATCH_TH_MULA 0x2000100b +#define MASK_TH_MULA 0xfe00707f +#define MATCH_TH_MULAH 0x2800100b +#define MASK_TH_MULAH 0xfe00707f +#define MATCH_TH_MULAW 0x2400100b +#define MASK_TH_MULAW 0xfe00707f +#define MATCH_TH_MULS 0x2200100b +#define MASK_TH_MULS 0xfe00707f +#define MATCH_TH_MULSH 0x2a00100b +#define MASK_TH_MULSH 0xfe00707f +#define MATCH_TH_MULSW 0x2600100b +#define MASK_TH_MULSW 0xfe00707f /* Vendor-specific (T-Head) XTheadSync instructions. */ #define MATCH_TH_SFENCE_VMAS 0x0400000b #define MASK_TH_SFENCE_VMAS 0xfe007fff @@ -2975,6 +2988,13 @@ DECLARE_INSN(th_l2cache_iall, MATCH_TH_L2CACHE_IALL, MASK_TH_L2CACHE_IALL) /* Vendor-specific (T-Head) XTheadCondMov instructions. */ DECLARE_INSN(th_mveqz, MATCH_TH_MVEQZ, MASK_TH_MVEQZ) DECLARE_INSN(th_mvnez, MATCH_TH_MVNEZ, MASK_TH_MVNEZ) +/* Vendor-specific (T-Head) XTheadMac instructions. */ +DECLARE_INSN(th_mula, MATCH_TH_MULA, MASK_TH_MULA) +DECLARE_INSN(th_mulah, MATCH_TH_MULAH, MASK_TH_MULAH) +DECLARE_INSN(th_mulaw, MATCH_TH_MULAW, MASK_TH_MULAW) +DECLARE_INSN(th_muls, MATCH_TH_MULS, MASK_TH_MULS) +DECLARE_INSN(th_mulsh, MATCH_TH_MULSH, MASK_TH_MULSH) +DECLARE_INSN(th_mulsw, MATCH_TH_MULSW, MASK_TH_MULSW) /* Vendor-specific (T-Head) XTheadSync instructions. */ DECLARE_INSN(th_sfence_vmas, MATCH_TH_SFENCE_VMAS, MASK_TH_SFENCE_VMAS) DECLARE_INSN(th_sync, MATCH_TH_SYNC, MASK_TH_SYNC) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index d0ff929..854269a 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -420,6 +420,7 @@ enum riscv_insn_class INSN_CLASS_XTHEADBS, INSN_CLASS_XTHEADCMO, INSN_CLASS_XTHEADCONDMOV, + INSN_CLASS_XTHEADMAC, INSN_CLASS_XTHEADSYNC, }; |