Update w/HEADusers/pmuldoon/c++compile

Problems:
	gdb/compile/compile.c
	gdb/cp-support.c
	gdb/cp-support.h
	gdb/gdbtypes.h
	gdb/language.c
	gdb/linespec.c

7 files changed, 47 insertions, 9 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 37e2486..c5788e2 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -55,6 +55,7 @@ typedef uint32_t aarch64_insn;
 #define AARCH64_FEATURE_SVE	0x10000000	/* SVE instructions.  */
 #define AARCH64_FEATURE_RCPC	0x20000000	/* RCPC instructions.  */
 #define AARCH64_FEATURE_COMPNUM	0x40000000	/* Complex # instructions.  */
+#define AARCH64_FEATURE_DOTPROD 0x080000000     /* Dot Product instructions.  */
 
 /* Architectures are the sum of the base and extensions.  */
 #define AARCH64_ARCH_V8		AARCH64_FEATURE (AARCH64_FEATURE_V8, \
@@ -508,6 +509,7 @@ enum aarch64_insn_class
   sve_size_hsd,
   sve_size_sd,
   testbranch,
+  dotproduct,
 };
 
 /* Opcode enumerators.  */
diff --git a/include/opcode/arc-func.h b/include/opcode/arc-func.h
index c794593..fb45b07 100644
--- a/include/opcode/arc-func.h
+++ b/include/opcode/arc-func.h
@@ -274,8 +274,21 @@ replace_disp12s (unsigned insn, int value ATTRIBUTE_UNUSED)
   insn = insn & ~0xfff;
   insn |= ((value >> 0) & 0x003f) << 6;
   insn |= ((value >> 6) & 0x003f) << 0;
-
   return insn;
 }
 
 #endif /* REPLACE_disp12s */
+
+/* mask  = 0000001111111111.  */
+#ifndef REPLACE_jli
+#define REPLACE_jli
+ATTRIBUTE_UNUSED static unsigned
+replace_jli (unsigned insn, int value)
+{
+  insn = insn & ~0x3ff;
+  insn |= ((value >> 0) & 0x03ff) << 0;
+
+  return insn;
+}
+
+#endif /* REPLACE_jli */
diff --git a/include/opcode/arc.h b/include/opcode/arc.h
index 69b2630..cd8b1a8 100644
--- a/include/opcode/arc.h
+++ b/include/opcode/arc.h
@@ -76,6 +76,7 @@ typedef enum
   PMU,
   POP,
   PUSH,
+  SJLI,
   STORE,
   SUB,
   ULTRAIP,
diff --git a/include/opcode/arm.h b/include/opcode/arm.h
index e2049a0..e11ac7c 100644
--- a/include/opcode/arm.h
+++ b/include/opcode/arm.h
@@ -93,7 +93,8 @@
 #define FPU_CRYPTO_EXT_ARMV8 0x00008000	/* Crypto for ARMv8.  */
 #define CRC_EXT_ARMV8	 0x00004000	/* CRC32 for ARMv8.  */
 #define FPU_VFP_EXT_ARMV8xD 0x00002000	/* Single-precision FP for ARMv8.  */
-#define FPU_NEON_EXT_RDMA 0x00001000     /* v8.1 Adv.SIMD extensions.  */
+#define FPU_NEON_EXT_RDMA 0x00001000	/* v8.1 Adv.SIMD extensions.  */
+#define FPU_NEON_EXT_DOTPROD 0x00000800	/* Dot Product extension.  */
 
 /* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
    defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
@@ -234,6 +235,8 @@
 #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
   ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \
 		      | FPU_NEON_EXT_RDMA)
+#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \
+  ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
 
 
 #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
diff --git a/include/opcode/avr.h b/include/opcode/avr.h
index 1c73022..2212816 100644
--- a/include/opcode/avr.h
+++ b/include/opcode/avr.h
@@ -110,6 +110,7 @@
    z - Z pointer register (for [e]lpm Rd,Z[+])
    M - immediate value from 0 to 255
    n - immediate value from 0 to 255 ( n = ~M ). Relocation impossible
+   N - immediate value from 0 to 255. Relocation impossible
    s - immediate value from 0 to 7
    P - Port address value from 0 to 63. (in, out)
    p - Port address value from 0 to 31. (cbi, sbi, sbic, sbis)
@@ -306,3 +307,7 @@ AVR_INSN (eijmp, "",   "1001010000011001", 1, AVR_ISA_EIND, 0x9419)
 /* DES instruction for encryption and decryption.  */
 AVR_INSN (des,  "E",   "10010100EEEE1011", 1, AVR_ISA_DES,  0x940B)
 
+/* Operands are evaluated by hand and won't pop new fux-ups.
+   The pseudo-insn is hidden behind NOP so that avr-dis.c don't see it. */
+AVR_INSN (__gcc_isr, "", "0000000000000000", 1, AVR_ISA_1200,  0x0)
+
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index c71a33a..ceae9ec 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -935,6 +935,9 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
    "+z" 5-bit rz register (OP_*_RZ)
    "+Z" 5-bit fz register (OP_*_FZ)
 
+   interAptiv MR2:
+   "-m" register list for SAVE/RESTORE instruction
+
    Enhanced VA Scheme:
    "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
 
@@ -1007,7 +1010,7 @@ mips_opcode_32bit_p (const struct mips_opcode *mo)
    Extension character sequences used so far ("-" followed by the
    following), for quick reference when adding more:
    "AB"
-   "abdstuvwxy"
+   "abdmstuvwxy"
 */
 
 /* These are the bits which may be set in the pinfo field of an
@@ -1214,7 +1217,7 @@ static const unsigned int mips_isa_table[] = {
 #undef ISAF
 
 /* Masks used for Chip specific instructions.  */
-#define INSN_CHIP_MASK		  0xc3ff4f60
+#define INSN_CHIP_MASK		  0xc7ff4f60
 
 /* Cavium Networks Octeon instructions.  */
 #define INSN_OCTEON		  0x00000800
@@ -1254,6 +1257,8 @@ static const unsigned int mips_isa_table[] = {
 #define INSN_LOONGSON_3A          0x00000400
 /* RMI Xlr instruction */
 #define INSN_XLR                 0x00000020
+/* Imagination interAptiv MR2.  */
+#define INSN_INTERAPTIV_MR2	  0x04000000
 
 /* DSP ASE */
 #define ASE_DSP			0x00000001
@@ -1286,6 +1291,9 @@ static const unsigned int mips_isa_table[] = {
 #define ASE_MIPS16E2		0x00008000
 /* MIPS16e2 MT ASE instructions.  */
 #define ASE_MIPS16E2_MT		0x00010000
+/* The Virtualization ASE has eXtended Physical Addressing (XPA)
+   instructions which are only valid when both ASEs are enabled.  */
+#define ASE_XPA_VIRT		0x00020000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -1356,6 +1364,7 @@ static const unsigned int mips_isa_table[] = {
 #define CPU_OCTEON2	6502
 #define CPU_OCTEON3	6503
 #define CPU_XLR     	887682   	/* decimal 'XLR'   */
+#define CPU_INTERAPTIV_MR2 736550	/* decimal 'IA2'  */
 
 /* Return true if the given CPU is included in INSN_* mask MASK.  */
 
@@ -1426,6 +1435,9 @@ cpu_is_member (int cpu, unsigned int mask)
     case CPU_XLR:
       return (mask & INSN_XLR) != 0;
 
+    case CPU_INTERAPTIV_MR2:
+      return (mask & INSN_INTERAPTIV_MR2) != 0;
+
     case CPU_MIPS32R6:
       return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
 
@@ -1847,6 +1859,8 @@ extern int bfd_mips_num_opcodes;
    "d" 5-bit EXT size, which becomes MSBD
        Requires that "b" occurs first to set position.
        Enforces: 0 < (pos+size) <= 32.
+   "n" 2-bit immediate (1 .. 4)
+   "o" 5-bit unsigned immediate * 16
    "r" 3-bit register
    "s" 3-bit ASMACRO select immediate
    "u" 16-bit unsigned immediate
@@ -1882,13 +1896,13 @@ extern int bfd_mips_num_opcodes;
    "0123456 89"
    ".[]<>"
    "ABCDEFGHI KLMNOPQRSTUVWXYZ"
-   "abcde   ijklm  pqrs uvwxyz"
+   "abcde   ijklmnopqrs uvwxyz"
   */
 
 /* Save/restore encoding for the args field when all 4 registers are
    either saved as arguments or saved/restored as statics.  */
-#define MIPS16_ALL_ARGS    0xe
-#define MIPS16_ALL_STATICS 0xb
+#define MIPS_SVRS_ALL_ARGS    0xe
+#define MIPS_SVRS_ALL_STATICS 0xb
 
 /* The following flags have the same value for the mips16 opcode
    table:
diff --git a/include/opcode/v850.h b/include/opcode/v850.h
index b20ef10..31f96d8 100644
--- a/include/opcode/v850.h
+++ b/include/opcode/v850.h
@@ -230,10 +230,10 @@ extern const struct v850_operand v850_operands[];
 /* The operand has '%' prefix.  */
 #define V850_OPERAND_PERCENT	0x200000
 
-/* This operand is a cache oparation.  */
+/* This operand is a cache operation.  */
 #define V850_OPERAND_CACHEOP	0x400000
 
-/* This operand is a prefetch oparation.  */
+/* This operand is a prefetch operation.  */
 #define V850_OPERAND_PREFOP	0x800000
 
 /* A PC-relative displacement where a positive value indicates a backwards displacement.  */