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| author | Tom de Vries <tdevries@suse.de> | 2024-11-23 12:20:34 +0100 |
|---|---|---|
| committer | Tom de Vries <tdevries@suse.de> | 2024-11-23 12:20:34 +0100 |
| commit | ac51afb51c00693bb19c6a6110e9a45d2e4f79b7 (patch) | |
| tree | b2fcf9ded59d04633dbb406083e2814c34e4e468 /gdb/arm-tdep.c | |
| parent | 63eedf3b09f73077ecff2118f45d1adb1391eddd (diff) | |
| download | binutils-ac51afb51c00693bb19c6a6110e9a45d2e4f79b7.zip binutils-ac51afb51c00693bb19c6a6110e9a45d2e4f79b7.tar.gz binutils-ac51afb51c00693bb19c6a6110e9a45d2e4f79b7.tar.bz2 | |
[gdb/contrib] Add two rules in common-misspellings.txt
Eli mentioned [1] that given that we use US English spelling in our
documentation, we should use "behavior" instead of "behaviour".
In wikipedia-common-misspellings.txt there's a rule:
...
behavour->behavior, behaviour
...
which leaves this as a choice.
Add an overriding rule to hardcode the choice to common-misspellings.txt:
...
behavour->behavior
...
and add a rule to rewrite behaviour into behavior:
...
behaviour->behavior
...
and re-run spellcheck.sh on gdb*.
Tested on x86_64-linux.
[1] https://sourceware.org/pipermail/gdb-patches/2024-November/213371.html
Diffstat (limited to 'gdb/arm-tdep.c')
| -rw-r--r-- | gdb/arm-tdep.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gdb/arm-tdep.c b/gdb/arm-tdep.c index 3450761..c27b2a2 100644 --- a/gdb/arm-tdep.c +++ b/gdb/arm-tdep.c @@ -588,7 +588,7 @@ static CORE_ADDR arm_analyze_prologue (struct gdbarch *gdbarch, CORE_ADDR prologue_start, CORE_ADDR prologue_end, struct arm_prologue_cache *cache, const arm_instruction_reader &insn_reader); -/* Architecture version for displaced stepping. This effects the behaviour of +/* Architecture version for displaced stepping. This effects the behavior of certain instructions, and really should not be hard-wired. */ #define DISPLACED_STEPPING_ARCH_VERSION 5 @@ -5574,7 +5574,7 @@ bx_write_pc (struct regcache *regs, ULONGEST val) } else { - /* Unpredictable behaviour. Try to do something sensible (switch to ARM + /* Unpredictable behavior. Try to do something sensible (switch to ARM mode, align dest to 4 bytes). */ warning (_("Single-stepping BX to non-word-aligned ARM instruction.")); regcache_cooked_write_unsigned (regs, ARM_PS_REGNUM, ps & ~t_bit); @@ -8776,7 +8776,7 @@ gdb_print_insn_arm (bfd_vma memaddr, disassemble_info *info) undefined instruction trap. ARM7TDMI is nominally ARMv4T, but does not in fact add the new instructions. The new undefined instructions in ARMv4 are all instructions that had no defined - behaviour in earlier chips. There is no guarantee that they will + behavior in earlier chips. There is no guarantee that they will raise an exception, but may be treated as NOP's. In practice, it may only safe to rely on instructions matching: @@ -8983,7 +8983,7 @@ arm_extract_return_value (struct type *type, struct regcache *regs, } else { - /* For a structure or union the behaviour is as if the value had + /* For a structure or union the behavior is as if the value had been stored to word-aligned memory and then loaded into registers with 32-bit load instruction(s). */ int len = type->length (); @@ -9058,7 +9058,7 @@ arm_return_in_memory (struct gdbarch *gdbarch, struct type *type) fields are not addressable, and all addressable subfields of unions always start at offset zero. - This function is based on the behaviour of GCC 2.95.1. + This function is based on the behavior of GCC 2.95.1. See: gcc/arm.c: arm_return_in_memory() for details. Note: All versions of GCC before GCC 2.95.2 do not set up the @@ -9213,7 +9213,7 @@ arm_store_return_value (struct type *type, struct regcache *regs, } else { - /* For a structure or union the behaviour is as if the value had + /* For a structure or union the behavior is as if the value had been stored to word-aligned memory and then loaded into registers with 32-bit load instruction(s). */ int len = type->length (); |