gdb/riscv: add support for vector registers in target descriptions

This commit adds support to RISC-V GDB for vector registers in the
incoming target description.

The vector registers should be described in a feature called
"org.gnu.gdb.riscv.vector", and should contain the register v0 to
v31.  There's no restriction on the size or type of these registers,
so the target description can set these up as it requires.

However, if the target feature is present then all of the registers
must be present, and they must all be the same size, these
requirements are, I believe, inline with the RISC-V vector extension.

The DWARF register numbers for the vector registers have been added,
and the code to map between GDB's internal numbering and the DWARF
numbering has been updated.

I have not yet added a feature/riscv/*.xml file for the vector
extension, the consequence of this is that we can't, right now, detect
vector registers on a native target, this patch is all about
supporting vectors on a remote target.

It is worth noting that I don't actually have access to a RISC-V
target with vectors, so the only testing that this patch has had has
been done using 'set tdesc filename ....' to load a target description
to which I have manually added the vector feature.  This has shown
that the vector register feature can be successfully parsed, and that
the registers show up in the expected register groups.

Additionally, the RISC-V vector extension is currently at v0.10, which
is also the v1.0 draft release.  However, this extension is not yet
finalised.  It is possible (but unlikely I think) that the register
set could change between now and the final release of the vector
extension.  If this were to happen then we would potentially end up
changing the requirements for the new org.gnu.gdb.riscv.vector
feature.  I really don't think it is likely that the register set will
change this late in the process, and even if it did, changing the
feature requirements will not be a problem as far as I am
concerned (when the alternative is GDB just continues without this
feature for now).

gdb/ChangeLog:

	* NEWS: Mention new target feature name.
	* arch/riscv.c (riscv_create_target_description): GDB doesn't
	currently create target descriptions containing vector registers.
	* arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member
	variable.
	<operator==>: Also compare vlen.
	<hash>: Also include vlen.
	* riscv-tdep.c (riscv_feature_name_vector): New static global.
	(struct riscv_vector_feature): New struct.
	(riscv_vector_feature): New static global.
	(riscv_register_reggroup_p): Ensure vector registers are part of
	the 'all' group, and part of the 'vector' group.
	(riscv_dwarf_reg_to_regnum): Handle vector registers.
	(riscv_gdbarch_init): Check vector register feature.
	* riscv-tdep.h: Add vector registers to GDB's internal register
	numbers, and to the DWARF register numbers.

gdb/doc/ChangeLog:

	* gdb.texinfo (RISC-V Features): Mention vector register feature.

2 files changed, 16 insertions, 2 deletions

diff --git a/gdb/arch/riscv.c b/gdb/arch/riscv.c
index 8fbcad1..85d60a3 100644
--- a/gdb/arch/riscv.c
+++ b/gdb/arch/riscv.c
@@ -84,6 +84,12 @@ riscv_create_target_description (const struct riscv_gdbarch_features features)
   else if (features.flen == 8)
     regnum = create_feature_riscv_64bit_fpu (tdesc.get (), regnum);
 
+  /* Currently GDB only supports vector features coming from remote
+     targets.  We don't support creating vector features on native targets
+     (yet).  */
+  if (features.vlen != 0)
+    error (_("unable to create vector feature"));
+
   return tdesc;
 }
 
diff --git a/gdb/arch/riscv.h b/gdb/arch/riscv.h
index faa038a..65a998b 100644
--- a/gdb/arch/riscv.h
+++ b/gdb/arch/riscv.h
@@ -46,13 +46,20 @@ struct riscv_gdbarch_features
      that there are no f-registers.  No other value is valid.  */
   int flen = 0;
 
+  /* The size of the v-registers in bytes.  The value 0 indicates a target
+     with no vector registers.  The minimum value for a standard compliant
+     target should be 16, but GDB doesn't currently mind, and will accept
+     any vector size.  */
+  int vlen = 0;
+
   /* When true this target is RV32E.  */
   bool embedded = false;
 
   /* Equality operator.  */
   bool operator== (const struct riscv_gdbarch_features &rhs) const
   {
-    return (xlen == rhs.xlen && flen == rhs.flen && embedded == rhs.embedded);
+    return (xlen == rhs.xlen && flen == rhs.flen
+	    && embedded == rhs.embedded && vlen == rhs.vlen);
   }
 
   /* Inequality operator.  */
@@ -66,7 +73,8 @@ struct riscv_gdbarch_features
   {
     std::size_t val = ((embedded ? 1 : 0) << 10
 		       | (xlen & 0x1f) << 5
-		       | (flen & 0x1f) << 0);
+		       | (flen & 0x1f) << 0
+		       | (vlen & 0xfff) << 11);
     return val;
   }
 };