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author | Jan Beulich <jbeulich@suse.com> | 2023-02-10 08:14:46 +0100 |
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committer | Jan Beulich <jbeulich@suse.com> | 2023-02-10 08:14:46 +0100 |
commit | 5dab1799d7079765845cfbe6b523bda3add93acb (patch) | |
tree | 5a2ed416dea2e191bc74ffb845c0bd33715dfca7 /gas | |
parent | ba3ffa6de0510892bf8020188d834f24ea8b7f75 (diff) | |
download | binutils-5dab1799d7079765845cfbe6b523bda3add93acb.zip binutils-5dab1799d7079765845cfbe6b523bda3add93acb.tar.gz binutils-5dab1799d7079765845cfbe6b523bda3add93acb.tar.bz2 |
x86: drop use of XOP2SOURCES
The few XOP insns which used it wrongly didn't have VexVVVV specified.
With that added, the only further missing piece to use more generic code
elsewhere is SwapSources - see e.g. the BMI2 insns for similar operand
patterns.
With the only users gone, drop the #define as well as the special case
code.
Diffstat (limited to 'gas')
-rw-r--r-- | gas/config/tc-i386.c | 40 |
1 files changed, 7 insertions, 33 deletions
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c index 01b10c1..c1338d2 100644 --- a/gas/config/tc-i386.c +++ b/gas/config/tc-i386.c @@ -2142,9 +2142,9 @@ operand_size_match (const insn_template *t) { unsigned int given = i.operands - j - 1; - /* For 4- and 5-operand insns VEX.W controls just the first two + /* For 4-operand and XOP insns VEX.W controls just the first two register operands. */ - if (t->opcode_modifier.vexsources) + if (t->opcode_modifier.vexsources || t->cpu_flags.bitfield.cpuxop) given = j < 2 ? 1 - j : j; if (t->operand_types[j].bitfield.class == Reg @@ -6933,7 +6933,8 @@ match_template (char mnem_suffix) if (!(size_match & MATCH_REVERSE)) continue; /* Try reversing direction of operands. */ - j = t->opcode_modifier.vexsources ? 1 : i.operands - 1; + j = t->opcode_modifier.vexsources + || t->cpu_flags.bitfield.cpuxop ? 1 : i.operands - 1; overlap0 = operand_type_and (i.types[0], operand_types[j]); overlap1 = operand_type_and (i.types[j], operand_types[0]); overlap2 = operand_type_and (i.types[1], operand_types[1]); @@ -6967,7 +6968,8 @@ match_template (char mnem_suffix) && (intel_syntax || intel_mnemonic)) found_reverse_match |= Opcode_FloatR; } - else if (t->opcode_modifier.vexsources) + else if (t->opcode_modifier.vexsources + || t->cpu_flags.bitfield.cpuxop) { found_reverse_match = Opcode_VexW; goto check_operands_345; @@ -8618,35 +8620,7 @@ build_modrm_byte (void) else mem = ~0; - if (i.tm.opcode_modifier.vexsources == XOP2SOURCES) - { - /* VEX.vvvv encodes one of the sources. */ - if (i.tm.opcode_modifier.vexw == VEXW0) - i.vex.register_specifier = i.op[0].regs; - else - i.vex.register_specifier = i.op[1].regs; - - /* Destination is a XMM register encoded in the ModRM.reg - and VEX.R bit. */ - i.rm.reg = i.op[2].regs->reg_num; - if ((i.op[2].regs->reg_flags & RegRex) != 0) - i.rex |= REX_R; - - /* ModRM.rm and VEX.B encodes the other source. */ - if (!i.mem_operands) - { - i.rm.mode = 3; - - if (i.tm.opcode_modifier.vexw == VEXW0) - i.rm.regmem = i.op[1].regs->reg_num; - else - i.rm.regmem = i.op[0].regs->reg_num; - - if ((i.op[1].regs->reg_flags & RegRex) != 0) - i.rex |= REX_B; - } - } - else if (i.tm.opcode_modifier.vexvvvv == VEXLWP) + if (i.tm.opcode_modifier.vexvvvv == VEXLWP) { i.vex.register_specifier = i.op[2].regs; if (!i.mem_operands) |