Arm64: check matching operands for predicated B16B16 insns

Except for bfml{a,s} their 1st and 3rd operands need to match - pass
the TIED macro argument accordingly. While doing that also slightly
re-arrange table entries, such that all predicated insns are close
together.

At the same time change the existing test source to actually use non-
matching operands for the respective bfml{a,s} forms.

6 files changed, 62 insertions, 36 deletions

diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.d b/gas/testsuite/gas/aarch64/bfloat16-1.d
index 582459b..4f1df80 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.d
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.d
@@ -50,24 +50,24 @@
 .*:	64222604 	bfclamp	z4.h, z16.h, z2.h
 .*:	64212688 	bfclamp	z8.h, z20.h, z1.h
 .*:	64202710 	bfclamp	z16.h, z24.h, z0.h
-.*:	65300000 	bfmla	z0.h, p0\/m, z0.h, z16.h
-.*:	65280421 	bfmla	z1.h, p1\/m, z1.h, z8.h
-.*:	65240842 	bfmla	z2.h, p2\/m, z2.h, z4.h
-.*:	65221084 	bfmla	z4.h, p4\/m, z4.h, z2.h
-.*:	65211908 	bfmla	z8.h, p6\/m, z8.h, z1.h
-.*:	65201e10 	bfmla	z16.h, p7\/m, z16.h, z0.h
+.*:	65300080 	bfmla	z0.h, p0\/m, z4.h, z16.h
+.*:	65280501 	bfmla	z1.h, p1\/m, z8.h, z8.h
+.*:	65240982 	bfmla	z2.h, p2\/m, z12.h, z4.h
+.*:	65221204 	bfmla	z4.h, p4\/m, z16.h, z2.h
+.*:	65211a88 	bfmla	z8.h, p6\/m, z20.h, z1.h
+.*:	65201f10 	bfmla	z16.h, p7\/m, z24.h, z0.h
 .*:	647e0a00 	bfmla	z0.h, z16.h, z6.h\[7\]
 .*:	64750901 	bfmla	z1.h, z8.h, z5.h\[6\]
 .*:	646409c2 	bfmla	z2.h, z14.h, z4.h\[4\]
 .*:	64320aa4 	bfmla	z4.h, z21.h, z2.h\[2\]
 .*:	64290988 	bfmla	z8.h, z12.h, z1.h\[1\]
 .*:	64200950 	bfmla	z16.h, z10.h, z0.h\[0\]
-.*:	65302000 	bfmls	z0.h, p0\/m, z0.h, z16.h
-.*:	65282421 	bfmls	z1.h, p1\/m, z1.h, z8.h
-.*:	65242842 	bfmls	z2.h, p2\/m, z2.h, z4.h
-.*:	65223084 	bfmls	z4.h, p4\/m, z4.h, z2.h
-.*:	65213908 	bfmls	z8.h, p6\/m, z8.h, z1.h
-.*:	65203e10 	bfmls	z16.h, p7\/m, z16.h, z0.h
+.*:	65302080 	bfmls	z0.h, p0\/m, z4.h, z16.h
+.*:	65282501 	bfmls	z1.h, p1\/m, z8.h, z8.h
+.*:	65242982 	bfmls	z2.h, p2\/m, z12.h, z4.h
+.*:	65223204 	bfmls	z4.h, p4\/m, z16.h, z2.h
+.*:	65213a88 	bfmls	z8.h, p6\/m, z20.h, z1.h
+.*:	65203f10 	bfmls	z16.h, p7\/m, z24.h, z0.h
 .*:	647e0e00 	bfmls	z0.h, z16.h, z6.h\[7\]
 .*:	64750d01 	bfmls	z1.h, z8.h, z5.h\[6\]
 .*:	64640dc2 	bfmls	z2.h, z14.h, z4.h\[4\]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-1.s b/gas/testsuite/gas/aarch64/bfloat16-1.s
index 5597d9e..b896913 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-1.s
+++ b/gas/testsuite/gas/aarch64/bfloat16-1.s
@@ -46,12 +46,13 @@ bfclamp z2.h, z12.h, z4.h
 bfclamp z4.h, z16.h, z2.h
 bfclamp z8.h, z20.h, z1.h
 bfclamp z16.h, z24.h, z0.h
-bfmla z0.h, p0/m, z0.h, z16.h
-bfmla z1.h, p1/m, z1.h, z8.h
-bfmla z2.h, p2/m, z2.h, z4.h
-bfmla z4.h, p4/m, z4.h, z2.h
-bfmla z8.h, p6/m, z8.h, z1.h
-bfmla z16.h, p7/m, z16.h, z0.h
+
+bfmla z0.h, p0/m, z4.h, z16.h
+bfmla z1.h, p1/m, z8.h, z8.h
+bfmla z2.h, p2/m, z12.h, z4.h
+bfmla z4.h, p4/m, z16.h, z2.h
+bfmla z8.h, p6/m, z20.h, z1.h
+bfmla z16.h, p7/m, z24.h, z0.h
 
 bfmla z0.h, z16.h, z6.h[7]
 bfmla z1.h, z8.h, z5.h[6]
@@ -60,12 +61,12 @@ bfmla z4.h, z21.h, z2.h[2]
 bfmla z8.h, z12.h, z1.h[1]
 bfmla z16.h, z10.h, z0.h[0]
 
-bfmls z0.h, p0/m, z0.h, z16.h
-bfmls z1.h, p1/m, z1.h, z8.h
-bfmls z2.h, p2/m, z2.h, z4.h
-bfmls z4.h, p4/m, z4.h, z2.h
-bfmls z8.h, p6/m, z8.h, z1.h
-bfmls z16.h, p7/m, z16.h, z0.h
+bfmls z0.h, p0/m, z4.h, z16.h
+bfmls z1.h, p1/m, z8.h, z8.h
+bfmls z2.h, p2/m, z12.h, z4.h
+bfmls z4.h, p4/m, z16.h, z2.h
+bfmls z8.h, p6/m, z20.h, z1.h
+bfmls z16.h, p7/m, z24.h, z0.h
 
 bfmls z0.h, z16.h, z6.h[7]
 bfmls z1.h, z8.h, z5.h[6]
diff --git a/gas/testsuite/gas/aarch64/bfloat16-bad.l b/gas/testsuite/gas/aarch64/bfloat16-bad.l
index 5a5192b..1519a29 100644
--- a/gas/testsuite/gas/aarch64/bfloat16-bad.l
+++ b/gas/testsuite/gas/aarch64/bfloat16-bad.l
@@ -41,24 +41,24 @@
 .*: Error: selected processor does not support `bfclamp z4.h,z16.h,z2.h'
 .*: Error: selected processor does not support `bfclamp z8.h,z20.h,z1.h'
 .*: Error: selected processor does not support `bfclamp z16.h,z24.h,z0.h'
-.*: Error: selected processor does not support `bfmla z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmla z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmla z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmla z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmla z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmla z16.h,p7\/m,z16.h,z0.h'
+.*: Error: selected processor does not support `bfmla .*
+.*: Error: selected processor does not support `bfmla .*
+.*: Error: selected processor does not support `bfmla .*
+.*: Error: selected processor does not support `bfmla .*
+.*: Error: selected processor does not support `bfmla .*
+.*: Error: selected processor does not support `bfmla .*
 .*: Error: selected processor does not support `bfmla z0.h,z16.h,z6.h\[7\]'
 .*: Error: selected processor does not support `bfmla z1.h,z8.h,z5.h\[6\]'
 .*: Error: selected processor does not support `bfmla z2.h,z14.h,z4.h\[4\]'
 .*: Error: selected processor does not support `bfmla z4.h,z21.h,z2.h\[2\]'
 .*: Error: selected processor does not support `bfmla z8.h,z12.h,z1.h\[1\]'
 .*: Error: selected processor does not support `bfmla z16.h,z10.h,z0.h\[0\]'
-.*: Error: selected processor does not support `bfmls z0.h,p0\/m,z0.h,z16.h'
-.*: Error: selected processor does not support `bfmls z1.h,p1\/m,z1.h,z8.h'
-.*: Error: selected processor does not support `bfmls z2.h,p2\/m,z2.h,z4.h'
-.*: Error: selected processor does not support `bfmls z4.h,p4\/m,z4.h,z2.h'
-.*: Error: selected processor does not support `bfmls z8.h,p6\/m,z8.h,z1.h'
-.*: Error: selected processor does not support `bfmls z16.h,p7\/m,z16.h,z0.h'
+.*: Error: selected processor does not support `bfmls .*
+.*: Error: selected processor does not support `bfmls .*
+.*: Error: selected processor does not support `bfmls .*
+.*: Error: selected processor does not support `bfmls .*
+.*: Error: selected processor does not support `bfmls .*
+.*: Error: selected processor does not support `bfmls .*
 .*: Error: selected processor does not support `bfmls z0.h,z16.h,z6.h\[7\]'
 .*: Error: selected processor does not support `bfmls z1.h,z8.h,z5.h\[6\]'
 .*: Error: selected processor does not support `bfmls z2.h,z14.h,z4.h\[4\]'
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.d b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
new file mode 100644
index 0000000..8f24dc6
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.d
@@ -0,0 +1,4 @@
+#name: Test Bfloat16 instructions with wrong operand combinations
+#as: -march=armv9.4-a
+#source: bfloat16-invalid.s
+#error_output: bfloat16-invalid.l
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.l b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
new file mode 100644
index 0000000..0b1354a
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.l
@@ -0,0 +1,8 @@
+.*: Assembler messages:
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfadd .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmax .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmaxnm .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmin .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfminnm .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfmul .*
+[^ :]+:[0-9]+: Error: operand 3 must be the same register as operand 1 -- `bfsub .*
diff --git a/gas/testsuite/gas/aarch64/bfloat16-invalid.s b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
new file mode 100644
index 0000000..a5bdfc8
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/bfloat16-invalid.s
@@ -0,0 +1,13 @@
+bfadd z0.h, p0/m, z1.h, z0.h
+
+bfmax z0.h, p0/m, z1.h, z0.h
+
+bfmaxnm z0.h, p0/m, z1.h, z0.h
+
+bfmin z0.h, p0/m, z1.h, z0.h
+
+bfminnm z0.h, p0/m, z1.h, z0.h
+
+bfmul z0.h, p0/m, z1.h, z0.h
+
+bfsub z0.h, p0/m, z1.h, z0.h