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| author | Jan Beulich <jbeulich@suse.com> | 2024-05-03 09:27:00 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2024-05-03 09:27:00 +0200 |
| commit | 1d026d6b19a95091b6a181bae7c6c3711f7f3ca3 (patch) | |
| tree | e56d884a3dbce93fb0629ddb218bff4a51eb7130 | |
| parent | 24187fb9c0d06f8084dfbd138e0b8b40d28ea024 (diff) | |
| download | binutils-1d026d6b19a95091b6a181bae7c6c3711f7f3ca3.zip binutils-1d026d6b19a95091b6a181bae7c6c3711f7f3ca3.tar.gz binutils-1d026d6b19a95091b6a181bae7c6c3711f7f3ca3.tar.bz2 | |
x86/APX: further extend SSE2AVX coverage
Since {vex}/{vex3} are respected on legacy mnemonics when -msse2avx is
in use, {evex} should be respected, too. So far this is the case only
for insns where eGPR-s can come into play. Extend coverage to insns with
only %xmm register and possibly immediate operands.
| -rw-r--r-- | gas/testsuite/gas/i386/sse2avx-evex.d | 451 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/sse2avx-evex.s | 522 | ||||
| -rw-r--r-- | gas/testsuite/gas/i386/x86-64.exp | 1 | ||||
| -rw-r--r-- | opcodes/i386-opc.tbl | 11 | ||||
| -rw-r--r-- | opcodes/i386-tbl.h | 480 |
5 files changed, 1235 insertions, 230 deletions
diff --git a/gas/testsuite/gas/i386/sse2avx-evex.d b/gas/testsuite/gas/i386/sse2avx-evex.d new file mode 100644 index 0000000..767128a --- /dev/null +++ b/gas/testsuite/gas/i386/sse2avx-evex.d @@ -0,0 +1,451 @@ +#as: -msse2avx +#objdump: -dw +#name: x86-64 SSE+ with \{evex\} prefix + +.*: file format .* + +Disassembly of section .text: + +0+ <sse2avx>: +[ ]*[a-f0-9]+: 62 f1 7c 08 5b f4 \{evex\} vcvtdq2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 5b 21 \{evex\} vcvtdq2ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 ff 08 e6 f4 \{evex\} vcvtpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 ff 08 e6 21 \{evex\} vcvtpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 5a f4 \{evex\} vcvtpd2ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 5a 21 \{evex\} vcvtpd2psx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7d 08 5b f4 \{evex\} vcvtps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7d 08 5b 21 \{evex\} vcvtps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 e6 f4 \{evex\} vcvttpd2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 e6 21 \{evex\} vcvttpd2dqx \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 5b f4 \{evex\} vcvttps2dq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 5b 21 \{evex\} vcvttps2dq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 28 f4 \{evex\} vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 28 21 \{evex\} vmovapd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7c 08 28 f4 \{evex\} vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 28 21 \{evex\} vmovaps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7d 08 6f 21 vmovdqa32 \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 6f 21 vmovdqu32 \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 16 f4 \{evex\} vmovshdup %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 16 21 \{evex\} vmovshdup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 12 f4 \{evex\} vmovsldup %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 12 21 \{evex\} vmovsldup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 10 f4 \{evex\} vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 10 21 \{evex\} vmovupd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7c 08 10 f4 \{evex\} vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 10 21 \{evex\} vmovups \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 1c f4 \{evex\} vpabsb %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 1c 21 \{evex\} vpabsb \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 1d f4 \{evex\} vpabsw %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 1d 21 \{evex\} vpabsw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 1e f4 \{evex\} vpabsd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 1e 21 \{evex\} vpabsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 4c f4 vrcp14ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 4c 21 vrcp14ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 4e f4 vrsqrt14ps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 4e 21 vrsqrt14ps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 51 f4 \{evex\} vsqrtpd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 51 21 \{evex\} vsqrtpd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7c 08 51 f4 \{evex\} vsqrtps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 51 21 \{evex\} vsqrtps \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 28 f4 \{evex\} vmovapd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 29 21 \{evex\} vmovapd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7c 08 28 f4 \{evex\} vmovaps %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 29 21 \{evex\} vmovaps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7d 08 6f f4 vmovdqa32 %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7d 08 7f 21 vmovdqa32 %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7e 08 6f f4 vmovdqu32 %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 7f 21 vmovdqu32 %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 fd 08 10 f4 \{evex\} vmovupd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 11 21 \{evex\} vmovupd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7c 08 10 f4 \{evex\} vmovups %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 11 21 \{evex\} vmovups %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7e 08 6f 21 vmovdqu32 \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 2a 21 \{evex\} vmovntdqa \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7d 08 e7 21 \{evex\} vmovntdq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 fd 08 2b 21 \{evex\} vmovntpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7c 08 2b 21 \{evex\} vmovntps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 cd 08 58 f4 \{evex\} vaddpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 58 31 \{evex\} vaddpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 58 f4 \{evex\} vaddps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 58 31 \{evex\} vaddps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 dc f4 \{evex\} vaesenc %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 dc 31 \{evex\} vaesenc \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 dd f4 \{evex\} vaesenclast %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 dd 31 \{evex\} vaesenclast \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 de f4 \{evex\} vaesdec %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 de 31 \{evex\} vaesdec \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 df f4 \{evex\} vaesdeclast %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 df 31 \{evex\} vaesdeclast \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 55 f4 \{evex\} vandnpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 55 31 \{evex\} vandnpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 55 f4 \{evex\} vandnps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 55 31 \{evex\} vandnps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 54 f4 \{evex\} vandpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 54 31 \{evex\} vandpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 54 f4 \{evex\} vandps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 54 31 \{evex\} vandps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5e f4 \{evex\} vdivpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5e 31 \{evex\} vdivpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5e f4 \{evex\} vdivps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5e 31 \{evex\} vdivps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 cf f4 \{evex\} vgf2p8mulb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 cf 31 \{evex\} vgf2p8mulb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5f f4 \{evex\} vmaxpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5f 31 \{evex\} vmaxpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5f f4 \{evex\} vmaxps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5f 31 \{evex\} vmaxps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5d f4 \{evex\} vminpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5d 31 \{evex\} vminpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5d f4 \{evex\} vminps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5d 31 \{evex\} vminps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 59 f4 \{evex\} vmulpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 59 31 \{evex\} vmulpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 59 f4 \{evex\} vmulps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 59 31 \{evex\} vmulps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 56 f4 \{evex\} vorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 56 31 \{evex\} vorpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 56 f4 \{evex\} vorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 56 31 \{evex\} vorps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 63 f4 \{evex\} vpacksswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 63 31 \{evex\} vpacksswb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 6b f4 \{evex\} vpackssdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 6b 31 \{evex\} vpackssdw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 67 f4 \{evex\} vpackuswb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 67 31 \{evex\} vpackuswb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 2b f4 \{evex\} vpackusdw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 2b 31 \{evex\} vpackusdw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fc f4 \{evex\} vpaddb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fc 31 \{evex\} vpaddb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fd f4 \{evex\} vpaddw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fd 31 \{evex\} vpaddw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fe f4 \{evex\} vpaddd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fe 31 \{evex\} vpaddd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 d4 f4 \{evex\} vpaddq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 d4 31 \{evex\} vpaddq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ec f4 \{evex\} vpaddsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ec 31 \{evex\} vpaddsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ed f4 \{evex\} vpaddsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ed 31 \{evex\} vpaddsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 dc f4 \{evex\} vpaddusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 dc 31 \{evex\} vpaddusb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 dd f4 \{evex\} vpaddusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 dd 31 \{evex\} vpaddusw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 db f4 vpandd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 db 31 vpandd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 df f4 vpandnd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 df 31 vpandnd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e0 f4 \{evex\} vpavgb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e0 31 \{evex\} vpavgb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e3 f4 \{evex\} vpavgw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e3 31 \{evex\} vpavgw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 f4 00 \{evex\} vpclmullqlqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 31 00 \{evex\} vpclmullqlqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 f4 01 \{evex\} vpclmulhqlqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 31 01 \{evex\} vpclmulhqlqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 f4 10 \{evex\} vpclmullqhqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 31 10 \{evex\} vpclmullqhqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 f4 11 \{evex\} vpclmulhqhqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 31 11 \{evex\} vpclmulhqhqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f5 f4 \{evex\} vpmaddwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f5 31 \{evex\} vpmaddwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 04 f4 \{evex\} vpmaddubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 04 31 \{evex\} vpmaddubsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3c f4 \{evex\} vpmaxsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3c 31 \{evex\} vpmaxsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ee f4 \{evex\} vpmaxsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ee 31 \{evex\} vpmaxsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3d f4 \{evex\} vpmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3d 31 \{evex\} vpmaxsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 de f4 \{evex\} vpmaxub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 de 31 \{evex\} vpmaxub \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3e f4 \{evex\} vpmaxuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3e 31 \{evex\} vpmaxuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3f f4 \{evex\} vpmaxud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3f 31 \{evex\} vpmaxud \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 38 f4 \{evex\} vpminsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 38 31 \{evex\} vpminsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ea f4 \{evex\} vpminsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ea 31 \{evex\} vpminsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 39 f4 \{evex\} vpminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 39 31 \{evex\} vpminsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 da f4 \{evex\} vpminub %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 da 31 \{evex\} vpminub \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3a f4 \{evex\} vpminuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3a 31 \{evex\} vpminuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3b f4 \{evex\} vpminud %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 3b 31 \{evex\} vpminud \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e4 f4 \{evex\} vpmulhuw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e4 31 \{evex\} vpmulhuw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 0b f4 \{evex\} vpmulhrsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 0b 31 \{evex\} vpmulhrsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e5 f4 \{evex\} vpmulhw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e5 31 \{evex\} vpmulhw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d5 f4 \{evex\} vpmullw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d5 31 \{evex\} vpmullw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 40 f4 \{evex\} vpmulld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 40 31 \{evex\} vpmulld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 f4 f4 \{evex\} vpmuludq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 f4 31 \{evex\} vpmuludq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 cd 08 28 f4 \{evex\} vpmuldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 cd 08 28 31 \{evex\} vpmuldq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 eb f4 vpord %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 eb 31 vpord \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f6 f4 \{evex\} vpsadbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f6 31 \{evex\} vpsadbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 00 f4 \{evex\} vpshufb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 00 31 \{evex\} vpshufb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f1 f4 \{evex\} vpsllw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f1 31 \{evex\} vpsllw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f2 f4 \{evex\} vpslld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f2 31 \{evex\} vpslld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 f3 f4 \{evex\} vpsllq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 f3 31 \{evex\} vpsllq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e1 f4 \{evex\} vpsraw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e1 31 \{evex\} vpsraw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e2 f4 \{evex\} vpsrad %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e2 31 \{evex\} vpsrad \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d1 f4 \{evex\} vpsrlw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d1 31 \{evex\} vpsrlw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d2 f4 \{evex\} vpsrld %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d2 31 \{evex\} vpsrld \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 d3 f4 \{evex\} vpsrlq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 d3 31 \{evex\} vpsrlq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f8 f4 \{evex\} vpsubb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f8 31 \{evex\} vpsubb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f9 f4 \{evex\} vpsubw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 f9 31 \{evex\} vpsubw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fa f4 \{evex\} vpsubd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 fa 31 \{evex\} vpsubd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 fb f4 \{evex\} vpsubq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 fb 31 \{evex\} vpsubq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e8 f4 \{evex\} vpsubsb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e8 31 \{evex\} vpsubsb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e9 f4 \{evex\} vpsubsw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 e9 31 \{evex\} vpsubsw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d8 f4 \{evex\} vpsubusb %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d8 31 \{evex\} vpsubusb \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d9 f4 \{evex\} vpsubusw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 d9 31 \{evex\} vpsubusw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 68 f4 \{evex\} vpunpckhbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 68 31 \{evex\} vpunpckhbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 69 f4 \{evex\} vpunpckhwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 69 31 \{evex\} vpunpckhwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 6a f4 \{evex\} vpunpckhdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 6a 31 \{evex\} vpunpckhdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 6d f4 \{evex\} vpunpckhqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 6d 31 \{evex\} vpunpckhqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 60 f4 \{evex\} vpunpcklbw %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 60 31 \{evex\} vpunpcklbw \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 61 f4 \{evex\} vpunpcklwd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 61 31 \{evex\} vpunpcklwd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 62 f4 \{evex\} vpunpckldq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 62 31 \{evex\} vpunpckldq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 6c f4 \{evex\} vpunpcklqdq %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 6c 31 \{evex\} vpunpcklqdq \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ef f4 vpxord %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4d 08 ef 31 vpxord \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5c f4 \{evex\} vsubpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 5c 31 \{evex\} vsubpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5c f4 \{evex\} vsubps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 5c 31 \{evex\} vsubps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 15 f4 \{evex\} vunpckhpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 15 31 \{evex\} vunpckhpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 15 f4 \{evex\} vunpckhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 15 31 \{evex\} vunpckhps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 14 f4 \{evex\} vunpcklpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 14 31 \{evex\} vunpcklpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 14 f4 \{evex\} vunpcklps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 14 31 \{evex\} vunpcklps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 57 f4 \{evex\} vxorpd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 57 31 \{evex\} vxorpd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 57 f4 \{evex\} vxorps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 57 31 \{evex\} vxorps \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7d 08 70 f4 64 \{evex\} vpshufd \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7d 08 70 31 64 \{evex\} vpshufd \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 70 f4 64 \{evex\} vpshufhw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 70 31 64 \{evex\} vpshufhw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: 62 f1 7f 08 70 f4 64 \{evex\} vpshuflw \$0x64,%xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7f 08 70 31 64 \{evex\} vpshuflw \$0x64,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: 62 f3 fd 08 09 f4 04 vrndscalepd \$0x4,%xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f3 fd 08 09 31 04 vrndscalepd \$0x4,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: 62 f3 7d 08 08 f4 04 vrndscaleps \$0x4,%xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f3 7d 08 08 31 04 vrndscaleps \$0x4,\(%rcx\),%xmm6 +[ ]*[a-f0-9]+: 62 f3 cd 08 ce f4 64 \{evex\} vgf2p8affineqb \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 cd 08 ce 31 64 \{evex\} vgf2p8affineqb \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 cd 08 cf f4 64 \{evex\} vgf2p8affineinvqb \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 cd 08 cf 31 64 \{evex\} vgf2p8affineinvqb \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 0f f4 64 \{evex\} vpalignr \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 0f 31 64 \{evex\} vpalignr \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 f4 64 \{evex\} vpclmulqdq \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 44 31 64 \{evex\} vpclmulqdq \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 c6 f4 64 \{evex\} vshufpd \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cd 08 c6 31 64 \{evex\} vshufpd \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 c6 f4 64 \{evex\} vshufps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 c6 31 64 \{evex\} vshufps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 2f f4 \{evex\} vcomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 2f 21 \{evex\} vcomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 e6 f4 \{evex\} vcvtdq2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7e 08 e6 21 \{evex\} vcvtdq2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 e6 21 \{evex\} vcvtdq2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7c 08 5a f4 \{evex\} vcvtps2pd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 5a 21 \{evex\} vcvtps2pd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 ff 08 12 f4 \{evex\} vmovddup %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 ff 08 12 21 \{evex\} vmovddup \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 20 f4 \{evex\} vpmovsxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 20 21 \{evex\} vpmovsxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 23 f4 \{evex\} vpmovsxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 23 21 \{evex\} vpmovsxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 25 f4 \{evex\} vpmovsxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 25 21 \{evex\} vpmovsxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 30 f4 \{evex\} vpmovzxbw %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 30 21 \{evex\} vpmovzxbw \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 33 f4 \{evex\} vpmovzxwd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 33 21 \{evex\} vpmovzxwd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 35 f4 \{evex\} vpmovzxdq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 35 21 \{evex\} vpmovzxdq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 2e f4 \{evex\} vucomisd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 fd 08 2e 21 \{evex\} vucomisd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 ff 08 10 21 \{evex\} vmovsd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 13 21 \{evex\} vmovlpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7c 08 13 21 \{evex\} vmovlps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 fd 08 17 21 \{evex\} vmovhpd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7c 08 17 21 \{evex\} vmovhps %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 ff 08 11 21 \{evex\} vmovsd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 fd 08 7e e1 \{evex\} vmovq %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 fd 08 6e e1 \{evex\} vmovq %rcx,%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 7e e1 \{evex\} vmovq %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 fd 08 6e e1 \{evex\} vmovq %rcx,%xmm4 +[ ]*[a-f0-9]+: 62 f1 fd 08 d6 21 \{evex\} vmovq %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 fe 08 7e 21 \{evex\} vmovq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7f 08 2d cc \{evex\} vcvtsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7f 08 2d 09 \{evex\} vcvtsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: 62 f1 7f 08 2c cc \{evex\} vcvttsd2si %xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7f 08 2c 09 \{evex\} vcvttsd2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: 62 f1 ff 08 2d cc \{evex\} vcvtsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 ff 08 2d 09 \{evex\} vcvtsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: 62 f1 ff 08 2c cc \{evex\} vcvttsd2si %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 ff 08 2c 09 \{evex\} vcvttsd2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: 62 f1 df 08 2a e1 \{evex\} vcvtsi2sd %rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 df 08 2a 21 \{evex\} vcvtsi2sdq \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 de 08 2a e1 \{evex\} vcvtsi2ss %rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 de 08 2a 21 \{evex\} vcvtsi2ssq \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 dd 08 22 e1 64 \{evex\} vpinsrq \$0x64,%rcx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 dd 08 22 21 64 \{evex\} vpinsrq \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 fd 08 16 e1 64 \{evex\} vpextrq \$0x64,%xmm4,%rcx +[ ]*[a-f0-9]+: 62 f3 fd 08 16 21 64 \{evex\} vpextrq \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 dd 08 12 21 \{evex\} vmovlpd \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5c 08 12 21 \{evex\} vmovlps \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 dd 08 16 21 \{evex\} vmovhpd \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5c 08 16 21 \{evex\} vmovhps \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 cd 08 0b f4 04 vrndscalesd \$0x4,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 cd 08 0b 31 04 vrndscalesd \$0x4,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 58 f4 \{evex\} vaddsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 58 31 \{evex\} vaddsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5a f4 \{evex\} vcvtsd2ss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5a 31 \{evex\} vcvtsd2ss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5e f4 \{evex\} vdivsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5e 31 \{evex\} vdivsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5f f4 \{evex\} vmaxsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5f 31 \{evex\} vmaxsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5d f4 \{evex\} vminsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5d 31 \{evex\} vminsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 59 f4 \{evex\} vmulsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 59 31 \{evex\} vmulsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 51 f4 \{evex\} vsqrtsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 51 31 \{evex\} vsqrtsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5c f4 \{evex\} vsubsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 5c 31 \{evex\} vsubsd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 58 f4 \{evex\} vaddss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 58 31 \{evex\} vaddss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5a f4 \{evex\} vcvtss2sd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5a 31 \{evex\} vcvtss2sd \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5e f4 \{evex\} vdivss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5e 31 \{evex\} vdivss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5f f4 \{evex\} vmaxss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5f 31 \{evex\} vmaxss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5d f4 \{evex\} vminss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5d 31 \{evex\} vminss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 59 f4 \{evex\} vmulss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 59 31 \{evex\} vmulss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 4d f4 vrcp14ss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 4d 31 vrcp14ss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 4f f4 vrsqrt14ss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 4d 08 4f 31 vrsqrt14ss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 51 f4 \{evex\} vsqrtss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 51 31 \{evex\} vsqrtss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5c f4 \{evex\} vsubss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 5c 31 \{evex\} vsubss \(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 2f f4 \{evex\} vcomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 2f 21 \{evex\} vcomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 21 f4 \{evex\} vpmovsxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 21 21 \{evex\} vpmovsxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 24 f4 \{evex\} vpmovsxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 24 21 \{evex\} vpmovsxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 31 f4 \{evex\} vpmovzxbd %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 31 21 \{evex\} vpmovzxbd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 34 f4 \{evex\} vpmovzxwq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 34 21 \{evex\} vpmovzxwq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7c 08 2e f4 \{evex\} vucomiss %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 7c 08 2e 21 \{evex\} vucomiss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 10 21 \{evex\} vmovss \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 11 21 \{evex\} vmovss %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7d 08 7e e1 \{evex\} vmovd %xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7d 08 7e 21 \{evex\} vmovd %xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 7d 08 6e e1 \{evex\} vmovd %ecx,%xmm4 +[ ]*[a-f0-9]+: 62 f1 7d 08 6e 21 \{evex\} vmovd \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7e 08 2d cc \{evex\} vcvtss2si %xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7e 08 2d 09 \{evex\} vcvtss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: 62 f1 7e 08 2c cc \{evex\} vcvttss2si %xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7e 08 2c 09 \{evex\} vcvttss2si \(%rcx\),%ecx +[ ]*[a-f0-9]+: 62 f1 fe 08 2d cc \{evex\} vcvtss2si %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 fe 08 2d 09 \{evex\} vcvtss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: 62 f1 fe 08 2c cc \{evex\} vcvttss2si %xmm4,%rcx +[ ]*[a-f0-9]+: 62 f1 fe 08 2c 09 \{evex\} vcvttss2si \(%rcx\),%rcx +[ ]*[a-f0-9]+: 62 f3 fd 08 17 e1 64 \{evex\} vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 17 21 64 \{evex\} vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f3 7d 08 16 e1 64 \{evex\} vpextrd \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 16 21 64 \{evex\} vpextrd \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f3 7d 08 17 e1 64 \{evex\} vextractps \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 17 21 64 \{evex\} vextractps \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 5f 08 2a e1 \{evex\} vcvtsi2sd %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5f 08 2a 21 \{evex\} vcvtsi2sdl \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5e 08 2a e1 \{evex\} vcvtsi2ss %ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5e 08 2a 21 \{evex\} vcvtsi2ssl \(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 4d 08 21 f4 64 \{evex\} vinsertps \$0x64,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 21 31 64 \{evex\} vinsertps \$0x64,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 0a f4 04 vrndscaless \$0x4,%xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f3 4d 08 0a 31 04 vrndscaless \$0x4,\(%rcx\),%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 22 f4 \{evex\} vpmovsxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 22 21 \{evex\} vpmovsxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f2 7d 08 32 f4 \{evex\} vpmovzxbq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f2 7d 08 32 21 \{evex\} vpmovzxbq \(%rcx\),%xmm4 +[ ]*[a-f0-9]+: 62 f1 7d 08 c5 cc 64 \{evex\} vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f1 7d 08 c5 cc 64 \{evex\} vpextrw \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 15 21 64 \{evex\} vpextrw \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f1 5d 08 c4 e1 64 \{evex\} vpinsrw \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 c4 e1 64 \{evex\} vpinsrw \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 c4 21 64 \{evex\} vpinsrw \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 7d 08 14 e1 64 \{evex\} vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 14 e1 64 \{evex\} vpextrb \$0x64,%xmm4,%ecx +[ ]*[a-f0-9]+: 62 f3 7d 08 14 21 64 \{evex\} vpextrb \$0x64,%xmm4,\(%rcx\) +[ ]*[a-f0-9]+: 62 f3 5d 08 20 e1 64 \{evex\} vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 5d 08 20 e1 64 \{evex\} vpinsrb \$0x64,%ecx,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f3 5d 08 20 21 64 \{evex\} vpinsrb \$0x64,\(%rcx\),%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 fe 08 7e f4 \{evex\} vmovq %xmm4,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 12 f4 \{evex\} vmovhlps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4c 08 16 f4 \{evex\} vmovlhps %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 cf 08 10 f4 \{evex\} vmovsd %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 4e 08 10 f4 \{evex\} vmovss %xmm4,%xmm6,%xmm6 +[ ]*[a-f0-9]+: 62 f1 5d 08 72 f4 64 \{evex\} vpslld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 73 fc 64 \{evex\} vpslldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 dd 08 73 f4 64 \{evex\} vpsllq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 71 f4 64 \{evex\} vpsllw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 72 e4 64 \{evex\} vpsrad \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 71 e4 64 \{evex\} vpsraw \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 72 d4 64 \{evex\} vpsrld \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 73 dc 64 \{evex\} vpsrldq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 dd 08 73 d4 64 \{evex\} vpsrlq \$0x64,%xmm4,%xmm4 +[ ]*[a-f0-9]+: 62 f1 5d 08 71 d4 64 \{evex\} vpsrlw \$0x64,%xmm4,%xmm4 +#pass diff --git a/gas/testsuite/gas/i386/sse2avx-evex.s b/gas/testsuite/gas/i386/sse2avx-evex.s new file mode 100644 index 0000000..191dab1 --- /dev/null +++ b/gas/testsuite/gas/i386/sse2avx-evex.s @@ -0,0 +1,522 @@ + .text + .sse_check warning +sse2avx: + +# Tests for op xmm/mem128, xmm + {evex} cvtdq2ps %xmm4,%xmm6 + {evex} cvtdq2ps (%rcx),%xmm4 + {evex} cvtpd2dq %xmm4,%xmm6 + {evex} cvtpd2dq (%rcx),%xmm4 + {evex} cvtpd2ps %xmm4,%xmm6 + {evex} cvtpd2ps (%rcx),%xmm4 + {evex} cvtps2dq %xmm4,%xmm6 + {evex} cvtps2dq (%rcx),%xmm4 + {evex} cvttpd2dq %xmm4,%xmm6 + {evex} cvttpd2dq (%rcx),%xmm4 + {evex} cvttps2dq %xmm4,%xmm6 + {evex} cvttps2dq (%rcx),%xmm4 + {evex} movapd %xmm4,%xmm6 + {evex} movapd (%rcx),%xmm4 + {evex} movaps %xmm4,%xmm6 + {evex} movaps (%rcx),%xmm4 + {evex} movdqa %xmm4,%xmm6 + {evex} movdqa (%rcx),%xmm4 + {evex} movdqu %xmm4,%xmm6 + {evex} movdqu (%rcx),%xmm4 + {evex} movshdup %xmm4,%xmm6 + {evex} movshdup (%rcx),%xmm4 + {evex} movsldup %xmm4,%xmm6 + {evex} movsldup (%rcx),%xmm4 + {evex} movupd %xmm4,%xmm6 + {evex} movupd (%rcx),%xmm4 + {evex} movups %xmm4,%xmm6 + {evex} movups (%rcx),%xmm4 + {evex} pabsb %xmm4,%xmm6 + {evex} pabsb (%rcx),%xmm4 + {evex} pabsw %xmm4,%xmm6 + {evex} pabsw (%rcx),%xmm4 + {evex} pabsd %xmm4,%xmm6 + {evex} pabsd (%rcx),%xmm4 + {evex} rcpps %xmm4,%xmm6 + {evex} rcpps (%rcx),%xmm4 + {evex} rsqrtps %xmm4,%xmm6 + {evex} rsqrtps (%rcx),%xmm4 + {evex} sqrtpd %xmm4,%xmm6 + {evex} sqrtpd (%rcx),%xmm4 + {evex} sqrtps %xmm4,%xmm6 + {evex} sqrtps (%rcx),%xmm4 + +# Tests for op xmm, xmm/mem128 + {evex} movapd %xmm4,%xmm6 + {evex} movapd %xmm4,(%rcx) + {evex} movaps %xmm4,%xmm6 + {evex} movaps %xmm4,(%rcx) + {evex} movdqa %xmm4,%xmm6 + {evex} movdqa %xmm4,(%rcx) + {evex} movdqu %xmm4,%xmm6 + {evex} movdqu %xmm4,(%rcx) + {evex} movupd %xmm4,%xmm6 + {evex} movupd %xmm4,(%rcx) + {evex} movups %xmm4,%xmm6 + {evex} movups %xmm4,(%rcx) + +# Tests for op mem128, xmm + {evex} lddqu (%rcx),%xmm4 + {evex} movntdqa (%rcx),%xmm4 + +# Tests for op xmm, mem128 + {evex} movntdq %xmm4,(%rcx) + {evex} movntpd %xmm4,(%rcx) + {evex} movntps %xmm4,(%rcx) + +# Tests for op xmm/mem128, xmm[, xmm] + {evex} addpd %xmm4,%xmm6 + {evex} addpd (%rcx),%xmm6 + {evex} addps %xmm4,%xmm6 + {evex} addps (%rcx),%xmm6 + {evex} aesenc %xmm4,%xmm6 + {evex} aesenc (%rcx),%xmm6 + {evex} aesenclast %xmm4,%xmm6 + {evex} aesenclast (%rcx),%xmm6 + {evex} aesdec %xmm4,%xmm6 + {evex} aesdec (%rcx),%xmm6 + {evex} aesdeclast %xmm4,%xmm6 + {evex} aesdeclast (%rcx),%xmm6 + {evex} andnpd %xmm4,%xmm6 + {evex} andnpd (%rcx),%xmm6 + {evex} andnps %xmm4,%xmm6 + {evex} andnps (%rcx),%xmm6 + {evex} andpd %xmm4,%xmm6 + {evex} andpd (%rcx),%xmm6 + {evex} andps %xmm4,%xmm6 + {evex} andps (%rcx),%xmm6 + {evex} divpd %xmm4,%xmm6 + {evex} divpd (%rcx),%xmm6 + {evex} divps %xmm4,%xmm6 + {evex} divps (%rcx),%xmm6 + {evex} gf2p8mulb %xmm4,%xmm6 + {evex} gf2p8mulb (%rcx),%xmm6 + {evex} maxpd %xmm4,%xmm6 + {evex} maxpd (%rcx),%xmm6 + {evex} maxps %xmm4,%xmm6 + {evex} maxps (%rcx),%xmm6 + {evex} minpd %xmm4,%xmm6 + {evex} minpd (%rcx),%xmm6 + {evex} minps %xmm4,%xmm6 + {evex} minps (%rcx),%xmm6 + {evex} mulpd %xmm4,%xmm6 + {evex} mulpd (%rcx),%xmm6 + {evex} mulps %xmm4,%xmm6 + {evex} mulps (%rcx),%xmm6 + {evex} orpd %xmm4,%xmm6 + {evex} orpd (%rcx),%xmm6 + {evex} orps %xmm4,%xmm6 + {evex} orps (%rcx),%xmm6 + {evex} packsswb %xmm4,%xmm6 + {evex} packsswb (%rcx),%xmm6 + {evex} packssdw %xmm4,%xmm6 + {evex} packssdw (%rcx),%xmm6 + {evex} packuswb %xmm4,%xmm6 + {evex} packuswb (%rcx),%xmm6 + {evex} packusdw %xmm4,%xmm6 + {evex} packusdw (%rcx),%xmm6 + {evex} paddb %xmm4,%xmm6 + {evex} paddb (%rcx),%xmm6 + {evex} paddw %xmm4,%xmm6 + {evex} paddw (%rcx),%xmm6 + {evex} paddd %xmm4,%xmm6 + {evex} paddd (%rcx),%xmm6 + {evex} paddq %xmm4,%xmm6 + {evex} paddq (%rcx),%xmm6 + {evex} paddsb %xmm4,%xmm6 + {evex} paddsb (%rcx),%xmm6 + {evex} paddsw %xmm4,%xmm6 + {evex} paddsw (%rcx),%xmm6 + {evex} paddusb %xmm4,%xmm6 + {evex} paddusb (%rcx),%xmm6 + {evex} paddusw %xmm4,%xmm6 + {evex} paddusw (%rcx),%xmm6 + {evex} pand %xmm4,%xmm6 + {evex} pand (%rcx),%xmm6 + {evex} pandn %xmm4,%xmm6 + {evex} pandn (%rcx),%xmm6 + {evex} pavgb %xmm4,%xmm6 + {evex} pavgb (%rcx),%xmm6 + {evex} pavgw %xmm4,%xmm6 + {evex} pavgw (%rcx),%xmm6 + {evex} pclmullqlqdq %xmm4,%xmm6 + {evex} pclmullqlqdq (%rcx),%xmm6 + {evex} pclmulhqlqdq %xmm4,%xmm6 + {evex} pclmulhqlqdq (%rcx),%xmm6 + {evex} pclmullqhqdq %xmm4,%xmm6 + {evex} pclmullqhqdq (%rcx),%xmm6 + {evex} pclmulhqhqdq %xmm4,%xmm6 + {evex} pclmulhqhqdq (%rcx),%xmm6 + {evex} pmaddwd %xmm4,%xmm6 + {evex} pmaddwd (%rcx),%xmm6 + {evex} pmaddubsw %xmm4,%xmm6 + {evex} pmaddubsw (%rcx),%xmm6 + {evex} pmaxsb %xmm4,%xmm6 + {evex} pmaxsb (%rcx),%xmm6 + {evex} pmaxsw %xmm4,%xmm6 + {evex} pmaxsw (%rcx),%xmm6 + {evex} pmaxsd %xmm4,%xmm6 + {evex} pmaxsd (%rcx),%xmm6 + {evex} pmaxub %xmm4,%xmm6 + {evex} pmaxub (%rcx),%xmm6 + {evex} pmaxuw %xmm4,%xmm6 + {evex} pmaxuw (%rcx),%xmm6 + {evex} pmaxud %xmm4,%xmm6 + {evex} pmaxud (%rcx),%xmm6 + {evex} pminsb %xmm4,%xmm6 + {evex} pminsb (%rcx),%xmm6 + {evex} pminsw %xmm4,%xmm6 + {evex} pminsw (%rcx),%xmm6 + {evex} pminsd %xmm4,%xmm6 + {evex} pminsd (%rcx),%xmm6 + {evex} pminub %xmm4,%xmm6 + {evex} pminub (%rcx),%xmm6 + {evex} pminuw %xmm4,%xmm6 + {evex} pminuw (%rcx),%xmm6 + {evex} pminud %xmm4,%xmm6 + {evex} pminud (%rcx),%xmm6 + {evex} pmulhuw %xmm4,%xmm6 + {evex} pmulhuw (%rcx),%xmm6 + {evex} pmulhrsw %xmm4,%xmm6 + {evex} pmulhrsw (%rcx),%xmm6 + {evex} pmulhw %xmm4,%xmm6 + {evex} pmulhw (%rcx),%xmm6 + {evex} pmullw %xmm4,%xmm6 + {evex} pmullw (%rcx),%xmm6 + {evex} pmulld %xmm4,%xmm6 + {evex} pmulld (%rcx),%xmm6 + {evex} pmuludq %xmm4,%xmm6 + {evex} pmuludq (%rcx),%xmm6 + {evex} pmuldq %xmm4,%xmm6 + {evex} pmuldq (%rcx),%xmm6 + {evex} por %xmm4,%xmm6 + {evex} por (%rcx),%xmm6 + {evex} psadbw %xmm4,%xmm6 + {evex} psadbw (%rcx),%xmm6 + {evex} pshufb %xmm4,%xmm6 + {evex} pshufb (%rcx),%xmm6 + {evex} psllw %xmm4,%xmm6 + {evex} psllw (%rcx),%xmm6 + {evex} pslld %xmm4,%xmm6 + {evex} pslld (%rcx),%xmm6 + {evex} psllq %xmm4,%xmm6 + {evex} psllq (%rcx),%xmm6 + {evex} psraw %xmm4,%xmm6 + {evex} psraw (%rcx),%xmm6 + {evex} psrad %xmm4,%xmm6 + {evex} psrad (%rcx),%xmm6 + {evex} psrlw %xmm4,%xmm6 + {evex} psrlw (%rcx),%xmm6 + {evex} psrld %xmm4,%xmm6 + {evex} psrld (%rcx),%xmm6 + {evex} psrlq %xmm4,%xmm6 + {evex} psrlq (%rcx),%xmm6 + {evex} psubb %xmm4,%xmm6 + {evex} psubb (%rcx),%xmm6 + {evex} psubw %xmm4,%xmm6 + {evex} psubw (%rcx),%xmm6 + {evex} psubd %xmm4,%xmm6 + {evex} psubd (%rcx),%xmm6 + {evex} psubq %xmm4,%xmm6 + {evex} psubq (%rcx),%xmm6 + {evex} psubsb %xmm4,%xmm6 + {evex} psubsb (%rcx),%xmm6 + {evex} psubsw %xmm4,%xmm6 + {evex} psubsw (%rcx),%xmm6 + {evex} psubusb %xmm4,%xmm6 + {evex} psubusb (%rcx),%xmm6 + {evex} psubusw %xmm4,%xmm6 + {evex} psubusw (%rcx),%xmm6 + {evex} punpckhbw %xmm4,%xmm6 + {evex} punpckhbw (%rcx),%xmm6 + {evex} punpckhwd %xmm4,%xmm6 + {evex} punpckhwd (%rcx),%xmm6 + {evex} punpckhdq %xmm4,%xmm6 + {evex} punpckhdq (%rcx),%xmm6 + {evex} punpckhqdq %xmm4,%xmm6 + {evex} punpckhqdq (%rcx),%xmm6 + {evex} punpcklbw %xmm4,%xmm6 + {evex} punpcklbw (%rcx),%xmm6 + {evex} punpcklwd %xmm4,%xmm6 + {evex} punpcklwd (%rcx),%xmm6 + {evex} punpckldq %xmm4,%xmm6 + {evex} punpckldq (%rcx),%xmm6 + {evex} punpcklqdq %xmm4,%xmm6 + {evex} punpcklqdq (%rcx),%xmm6 + {evex} pxor %xmm4,%xmm6 + {evex} pxor (%rcx),%xmm6 + {evex} subpd %xmm4,%xmm6 + {evex} subpd (%rcx),%xmm6 + {evex} subps %xmm4,%xmm6 + {evex} subps (%rcx),%xmm6 + {evex} unpckhpd %xmm4,%xmm6 + {evex} unpckhpd (%rcx),%xmm6 + {evex} unpckhps %xmm4,%xmm6 + {evex} unpckhps (%rcx),%xmm6 + {evex} unpcklpd %xmm4,%xmm6 + {evex} unpcklpd (%rcx),%xmm6 + {evex} unpcklps %xmm4,%xmm6 + {evex} unpcklps (%rcx),%xmm6 + {evex} xorpd %xmm4,%xmm6 + {evex} xorpd (%rcx),%xmm6 + {evex} xorps %xmm4,%xmm6 + {evex} xorps (%rcx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm + {evex} pshufd $100,%xmm4,%xmm6 + {evex} pshufd $100,(%rcx),%xmm6 + {evex} pshufhw $100,%xmm4,%xmm6 + {evex} pshufhw $100,(%rcx),%xmm6 + {evex} pshuflw $100,%xmm4,%xmm6 + {evex} pshuflw $100,(%rcx),%xmm6 + {evex} roundpd $4,%xmm4,%xmm6 + {evex} roundpd $4,(%rcx),%xmm6 + {evex} roundps $4,%xmm4,%xmm6 + {evex} roundps $4,(%rcx),%xmm6 + +# Tests for op imm8, xmm/mem128, xmm[, xmm] + {evex} gf2p8affineqb $100,%xmm4,%xmm6 + {evex} gf2p8affineqb $100,(%rcx),%xmm6 + {evex} gf2p8affineinvqb $100,%xmm4,%xmm6 + {evex} gf2p8affineinvqb $100,(%rcx),%xmm6 + {evex} palignr $100,%xmm4,%xmm6 + {evex} palignr $100,(%rcx),%xmm6 + {evex} pclmulqdq $100,%xmm4,%xmm6 + {evex} pclmulqdq $100,(%rcx),%xmm6 + {evex} shufpd $100,%xmm4,%xmm6 + {evex} shufpd $100,(%rcx),%xmm6 + {evex} shufps $100,%xmm4,%xmm6 + {evex} shufps $100,(%rcx),%xmm6 + +# Tests for op xmm/mem64, xmm + {evex} comisd %xmm4,%xmm6 + {evex} comisd (%rcx),%xmm4 + {evex} cvtdq2pd %xmm4,%xmm6 + {evex} cvtdq2pd (%rcx),%xmm4 + {evex} cvtpi2pd (%rcx),%xmm4 + {evex} cvtps2pd %xmm4,%xmm6 + {evex} cvtps2pd (%rcx),%xmm4 + {evex} movddup %xmm4,%xmm6 + {evex} movddup (%rcx),%xmm4 + {evex} pmovsxbw %xmm4,%xmm6 + {evex} pmovsxbw (%rcx),%xmm4 + {evex} pmovsxwd %xmm4,%xmm6 + {evex} pmovsxwd (%rcx),%xmm4 + {evex} pmovsxdq %xmm4,%xmm6 + {evex} pmovsxdq (%rcx),%xmm4 + {evex} pmovzxbw %xmm4,%xmm6 + {evex} pmovzxbw (%rcx),%xmm4 + {evex} pmovzxwd %xmm4,%xmm6 + {evex} pmovzxwd (%rcx),%xmm4 + {evex} pmovzxdq %xmm4,%xmm6 + {evex} pmovzxdq (%rcx),%xmm4 + {evex} ucomisd %xmm4,%xmm6 + {evex} ucomisd (%rcx),%xmm4 + +# Tests for op mem64, xmm + {evex} movsd (%rcx),%xmm4 + +# Tests for op xmm, mem64 + {evex} movlpd %xmm4,(%rcx) + {evex} movlps %xmm4,(%rcx) + {evex} movhpd %xmm4,(%rcx) + {evex} movhps %xmm4,(%rcx) + {evex} movsd %xmm4,(%rcx) + +# Tests for op xmm, regq/mem64 +# Tests for op regq/mem64, xmm + {evex} movd %xmm4,%rcx + {evex} movd %rcx,%xmm4 + {evex} movq %xmm4,%rcx + {evex} movq %rcx,%xmm4 + {evex} movq %xmm4,(%rcx) + {evex} movq (%rcx),%xmm4 + +# Tests for op xmm/mem64, regl + {evex} cvtsd2si %xmm4,%ecx + {evex} cvtsd2si (%rcx),%ecx + {evex} cvttsd2si %xmm4,%ecx + {evex} cvttsd2si (%rcx),%ecx + +# Tests for op xmm/mem64, regq + {evex} cvtsd2si %xmm4,%rcx + {evex} cvtsd2si (%rcx),%rcx + {evex} cvttsd2si %xmm4,%rcx + {evex} cvttsd2si (%rcx),%rcx + +# Tests for op regq/mem64, xmm[, xmm] + {evex} cvtsi2sdq %rcx,%xmm4 + {evex} cvtsi2sdq (%rcx),%xmm4 + {evex} cvtsi2ssq %rcx,%xmm4 + {evex} cvtsi2ssq (%rcx),%xmm4 + +# Tests for op imm8, regq/mem64, xmm[, xmm] + {evex} pinsrq $100,%rcx,%xmm4 + {evex} pinsrq $100,(%rcx),%xmm4 + +# Testsf for op imm8, xmm, regq/mem64 + {evex} pextrq $100,%xmm4,%rcx + {evex} pextrq $100,%xmm4,(%rcx) + +# Tests for op mem64, xmm[, xmm] + {evex} movlpd (%rcx),%xmm4 + {evex} movlps (%rcx),%xmm4 + {evex} movhpd (%rcx),%xmm4 + {evex} movhps (%rcx),%xmm4 + +# Tests for op imm8, xmm/mem64, xmm[, xmm] + {evex} roundsd $4,%xmm4,%xmm6 + {evex} roundsd $4,(%rcx),%xmm6 + +# Tests for op xmm/mem64, xmm[, xmm] + {evex} addsd %xmm4,%xmm6 + {evex} addsd (%rcx),%xmm6 + {evex} cvtsd2ss %xmm4,%xmm6 + {evex} cvtsd2ss (%rcx),%xmm6 + {evex} divsd %xmm4,%xmm6 + {evex} divsd (%rcx),%xmm6 + {evex} maxsd %xmm4,%xmm6 + {evex} maxsd (%rcx),%xmm6 + {evex} minsd %xmm4,%xmm6 + {evex} minsd (%rcx),%xmm6 + {evex} mulsd %xmm4,%xmm6 + {evex} mulsd (%rcx),%xmm6 + {evex} sqrtsd %xmm4,%xmm6 + {evex} sqrtsd (%rcx),%xmm6 + {evex} subsd %xmm4,%xmm6 + {evex} subsd (%rcx),%xmm6 + +# Tests for op xmm/mem32, xmm[, xmm] + {evex} addss %xmm4,%xmm6 + {evex} addss (%rcx),%xmm6 + {evex} cvtss2sd %xmm4,%xmm6 + {evex} cvtss2sd (%rcx),%xmm6 + {evex} divss %xmm4,%xmm6 + {evex} divss (%rcx),%xmm6 + {evex} maxss %xmm4,%xmm6 + {evex} maxss (%rcx),%xmm6 + {evex} minss %xmm4,%xmm6 + {evex} minss (%rcx),%xmm6 + {evex} mulss %xmm4,%xmm6 + {evex} mulss (%rcx),%xmm6 + {evex} rcpss %xmm4,%xmm6 + {evex} rcpss (%rcx),%xmm6 + {evex} rsqrtss %xmm4,%xmm6 + {evex} rsqrtss (%rcx),%xmm6 + {evex} sqrtss %xmm4,%xmm6 + {evex} sqrtss (%rcx),%xmm6 + {evex} subss %xmm4,%xmm6 + {evex} subss (%rcx),%xmm6 + +# Tests for op xmm/mem32, xmm + {evex} comiss %xmm4,%xmm6 + {evex} comiss (%rcx),%xmm4 + {evex} pmovsxbd %xmm4,%xmm6 + {evex} pmovsxbd (%rcx),%xmm4 + {evex} pmovsxwq %xmm4,%xmm6 + {evex} pmovsxwq (%rcx),%xmm4 + {evex} pmovzxbd %xmm4,%xmm6 + {evex} pmovzxbd (%rcx),%xmm4 + {evex} pmovzxwq %xmm4,%xmm6 + {evex} pmovzxwq (%rcx),%xmm4 + {evex} ucomiss %xmm4,%xmm6 + {evex} ucomiss (%rcx),%xmm4 + +# Tests for op mem32, xmm + {evex} movss (%rcx),%xmm4 + +# Tests for op xmm, mem32 + {evex} movss %xmm4,(%rcx) + +# Tests for op xmm, regl/mem32 +# Tests for op regl/mem32, xmm + {evex} movd %xmm4,%ecx + {evex} movd %xmm4,(%rcx) + {evex} movd %ecx,%xmm4 + {evex} movd (%rcx),%xmm4 + +# Tests for op xmm/mem32, regl + {evex} cvtss2si %xmm4,%ecx + {evex} cvtss2si (%rcx),%ecx + {evex} cvttss2si %xmm4,%ecx + {evex} cvttss2si (%rcx),%ecx + +# Tests for op xmm/mem32, regq + {evex} cvtss2si %xmm4,%rcx + {evex} cvtss2si (%rcx),%rcx + {evex} cvttss2si %xmm4,%rcx + {evex} cvttss2si (%rcx),%rcx + +# Tests for op imm8, xmm, regq/mem32 + {evex} extractps $100,%xmm4,%rcx + {evex} extractps $100,%xmm4,(%rcx) + +# Tests for op imm8, xmm, regl/mem32 + {evex} pextrd $100,%xmm4,%ecx + {evex} pextrd $100,%xmm4,(%rcx) + {evex} extractps $100,%xmm4,%ecx + {evex} extractps $100,%xmm4,(%rcx) + +# Tests for op regl/mem32, xmm[, xmm] + {evex} cvtsi2sd %ecx,%xmm4 + {evex} cvtsi2sdl (%rcx),%xmm4 + {evex} cvtsi2ss %ecx,%xmm4 + {evex} cvtsi2ssl (%rcx),%xmm4 + +# Tests for op imm8, xmm/mem32, xmm[, xmm] + {evex} insertps $100,%xmm4,%xmm6 + {evex} insertps $100,(%rcx),%xmm6 + {evex} roundss $4,%xmm4,%xmm6 + {evex} roundss $4,(%rcx),%xmm6 + +# Tests for op xmm/m16, xmm + {evex} pmovsxbq %xmm4,%xmm6 + {evex} pmovsxbq (%rcx),%xmm4 + {evex} pmovzxbq %xmm4,%xmm6 + {evex} pmovzxbq (%rcx),%xmm4 + +# Tests for op imm8, xmm, regl/mem16 + {evex} pextrw $100,%xmm4,%ecx + {evex} pextrw $100,%xmm4,%rcx + {evex} pextrw $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem16, xmm[, xmm] + {evex} pinsrw $100,%ecx,%xmm4 + {evex} pinsrw $100,%rcx,%xmm4 + {evex} pinsrw $100,(%rcx),%xmm4 + +# Tests for op imm8, xmm, regl/mem8 + {evex} pextrb $100,%xmm4,%ecx + {evex} pextrb $100,%xmm4,%rcx + {evex} pextrb $100,%xmm4,(%rcx) + +# Tests for op imm8, regl/mem8, xmm[, xmm] + {evex} pinsrb $100,%ecx,%xmm4 + {evex} pinsrb $100,%rcx,%xmm4 + {evex} pinsrb $100,(%rcx),%xmm4 + +# Tests for op xmm, xmm + {evex} movq %xmm4,%xmm6 + +# Tests for op xmm, xmm[, xmm] + {evex} movhlps %xmm4,%xmm6 + {evex} movlhps %xmm4,%xmm6 + {evex} movsd %xmm4,%xmm6 + {evex} movss %xmm4,%xmm6 + +# Tests for op imm8, xmm[, xmm] + {evex} pslld $100,%xmm4 + {evex} pslldq $100,%xmm4 + {evex} psllq $100,%xmm4 + {evex} psllw $100,%xmm4 + {evex} psrad $100,%xmm4 + {evex} psraw $100,%xmm4 + {evex} psrld $100,%xmm4 + {evex} psrldq $100,%xmm4 + {evex} psrlq $100,%xmm4 + {evex} psrlw $100,%xmm4 diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp index 627626a..a50865f 100644 --- a/gas/testsuite/gas/i386/x86-64.exp +++ b/gas/testsuite/gas/i386/x86-64.exp @@ -391,6 +391,7 @@ run_dump_test "x86-64-apx-nf" run_dump_test "x86-64-apx-nf-intel" run_dump_test "x86-64-apx_f-evex" run_dump_test "sse2avx-apx" +run_dump_test "sse2avx-evex" run_dump_test "x86-64-avx512f-rcigrz-intel" run_dump_test "x86-64-avx512f-rcigrz" run_dump_test "x86-64-clwb" diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl index e866d77..e488bd2 100644 --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -1170,11 +1170,11 @@ maxss<SSE>, 0xf30f5f, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unsp minps<SSE>, 0x0f5d, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } minss<SSE>, 0xf30f5d, <SSE:cpu>, Modrm|<SSE:scal>|<SSE:vvvv>|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movaps<SSE>, 0x0f28, <SSE:cpu>, D|Modrm|<SSE:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -movhlps<sse>, 0x0f12, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } +movhlps<SSE>, 0x0f12, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM, RegXMM } movhps, 0x16, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexVVVV|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } movhps, 0x17, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } movhps, 0xf16, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } -movlhps<sse>, 0x0f16, <sse:cpu>, Modrm|<sse:attr>|<sse:vvvv>|NoSuf, { RegXMM, RegXMM } +movlhps<SSE>, 0x0f16, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM, RegXMM } movlps, 0x12, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexVVVV|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } movlps, 0x13, AVX|AVX512F, Modrm|Vex128|EVex128|Space0F|VexW0|Disp8MemShift=3|NoSuf|SSE2AVX, { RegXMM, Qword|Unspecified|BaseIndex } movlps, 0xf12, SSE, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex, RegXMM } @@ -1183,7 +1183,7 @@ movntps<SSE>, 0x0f2b, <SSE:cpu>, Modrm|<SSE:attr>|NoSuf, { RegXMM, Xmmword|Unspe movntq, 0xfe7, SSE|3dnowA, Modrm|NoSuf, { RegMMX, Qword|Unspecified|BaseIndex } movntdq<SSE2D>, 0x660fe7, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { RegXMM, Xmmword|Unspecified|BaseIndex } movss, 0xf310, AVX|AVX512F, D|Modrm|VexLIG|EVexLIG|Space0F|VexW0|Disp8MemShift=2|NoSuf|SSE2AVX, { Dword|Unspecified|BaseIndex, RegXMM } -movss, 0xf310, AVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movss, 0xf310, AVX|AVX512F, D|Modrm|VexLIG|EVexLIG|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { RegXMM, RegXMM } movss, 0xf30f10, SSE, D|Modrm|NoSuf, { Dword|Unspecified|BaseIndex|RegXMM, RegXMM } movups<SSE>, 0x0f10, <SSE:cpu>, D|Modrm|<SSE:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulps<SSE>, 0x0f59, <SSE:cpu>, Modrm|<SSE:attr>|<SSE:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1278,6 +1278,7 @@ movntpd<SSE2Q>, 0x660f2b, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|NoSuf, { RegXMM, Xmmwo movsd, 0xf210, AVX, D|Modrm|VexLIG|Space0F|VexW0|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } movsd, 0xf210, AVX512F, D|Modrm|EVexLIG|Space0F|VexW1|Disp8MemShift=3|NoSuf|SSE2AVX, { Qword|Unspecified|BaseIndex, RegXMM } movsd, 0xf210, AVX, D|Modrm|VexLIG|Space0F|VexVVVV|VexW0|NoSuf|SSE2AVX, { RegXMM, RegXMM } +movsd, 0xf210, AVX512F, D|Modrm|EVexLIG|Space0F|VexVVVV|VexW1|NoSuf|SSE2AVX, { RegXMM, RegXMM } movsd, 0xf20f10, SSE2, D|Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } movupd<SSE2Q>, 0x660f10, <SSE2Q:cpu>, D|Modrm|<SSE2Q:attr>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } mulpd<SSE2Q>, 0x660f59, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1318,8 +1319,8 @@ pmuludq, 0xff4, SSE2, Modrm|NoSuf, { Qword|Unspecified|BaseIndex|RegMMX, RegMMX pshufd<SSE2D>, 0x660f70, <SSE2D:cpu>, Modrm|<SSE2D:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } pshufhw<SSE2BW>, 0xf30f70, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } pshuflw<SSE2BW>, 0xf20f70, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|NoSuf, { Imm8|Imm8S, RegXMM|Unspecified|BaseIndex, RegXMM } -pslldq<sse2>, 0x660f73/7, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM } -psrldq<sse2>, 0x660f73/3, <sse2:cpu>, Modrm|<sse2:attr>|<sse2:vvvv>|NoSuf, { Imm8, RegXMM } +pslldq<SSE2BW>, 0x660f73/7, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { Imm8, RegXMM } +psrldq<SSE2BW>, 0x660f73/3, <SSE2BW:cpu>, Modrm|<SSE2BW:attr>|<SSE2BW:vvvv>|NoSuf, { Imm8, RegXMM } punpckhqdq<SSE2Q>, 0x660f6d, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } punpcklqdq<SSE2Q>, 0x660f6c, <SSE2Q:cpu>, Modrm|<SSE2Q:attr>|<SSE2Q:vvvv>|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h index d66e7fe..a327a89 100644 --- a/opcodes/i386-tbl.h +++ b/opcodes/i386-tbl.h @@ -10644,10 +10644,10 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_movhlps, 0x12, 2, SPACE_0F, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 1, 1, 1, 0, 0, 1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -10694,10 +10694,10 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_movlhps, 0x16, 2, SPACE_0F, None, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 1, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 1, 1, 1, 0, 0, 1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, 0 }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -10824,10 +10824,10 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_movss, 0x10, 2, SPACE_0F, None, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, - 0, 0, 0, 3, 1, 1, 2, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, + 0, 0, 0, 3, 1, 1, 2, 0, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, - { { 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0 } }, { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0 } }, { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0 } }, { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -12844,6 +12844,16 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_movsd, 0x10, 2, SPACE_0F, None, { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 2, 3, 0, 1, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0 }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } } } }, + { MN_movsd, 0x10, 2, SPACE_0F, None, + { 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -13776,6 +13786,16 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_pslldq, 0x73, 2, SPACE_0F, 7, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 0, 1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, + 0 }, + { { 35, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } } } }, + { MN_pslldq, 0x73, 2, SPACE_0F, 7, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -13796,6 +13816,16 @@ static const insn_template i386_optab[] = 1, 0, 0, 0, 0, 0 } } } }, { MN_psrldq, 0x73, 2, SPACE_0F, 3, { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 1, 1, 1, 0, 1, 2, 0, 0, 0, 0, 4, 0, 0, 0, 0, 0, + 0 }, + { { 35, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0 } }, + { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, + { { { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0 } }, + { { 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 1, 0, 0, 0, 0, 0 } } } }, + { MN_psrldq, 0x73, 2, SPACE_0F, 3, + { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, { { 17, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } }, @@ -43076,225 +43106,225 @@ static const i386_op_off_t i386_op_sets[] = 1274, 1276, 1278, 1280, 1282, 1284, 1286, 1288, 1290, 1292, 1294, 1296, 1298, 1300, 1302, 1304, 1306, 1309, 1312, 1318, 1321, 1324, 1327, 1330, - 1333, 1336, 1339, 1344, 1349, 1351, 1354, 1358, - 1361, 1364, 1367, 1370, 1373, 1376, 1379, 1382, - 1385, 1388, 1391, 1394, 1397, 1399, 1402, 1404, - 1405, 1408, 1410, 1412, 1414, 1417, 1419, 1420, - 1422, 1425, 1427, 1429, 1431, 1433, 1434, 1435, - 1439, 1441, 1444, 1447, 1449, 1451, 1454, 1457, - 1459, 1461, 1463, 1465, 1467, 1469, 1472, 1475, - 1477, 1479, 1481, 1482, 1483, 1486, 1488, 1489, - 1490, 1491, 1492, 1493, 1494, 1496, 1498, 1499, - 1500, 1501, 1502, 1505, 1508, 1511, 1514, 1517, - 1520, 1523, 1526, 1529, 1533, 1537, 1541, 1544, - 1547, 1550, 1554, 1558, 1562, 1565, 1567, 1569, - 1573, 1577, 1579, 1581, 1585, 1587, 1589, 1591, - 1594, 1598, 1600, 1602, 1608, 1611, 1614, 1616, - 1622, 1625, 1628, 1631, 1633, 1635, 1638, 1641, - 1643, 1645, 1648, 1651, 1653, 1655, 1657, 1659, - 1661, 1664, 1666, 1668, 1670, 1672, 1674, 1677, - 1679, 1681, 1684, 1686, 1689, 1691, 1693, 1697, - 1701, 1703, 1705, 1709, 1710, 1711, 1712, 1713, - 1714, 1715, 1716, 1717, 1719, 1721, 1723, 1725, - 1727, 1729, 1731, 1733, 1735, 1737, 1739, 1741, - 1743, 1745, 1747, 1749, 1751, 1753, 1754, 1755, - 1757, 1759, 1761, 1763, 1764, 1765, 1766, 1767, - 1769, 1772, 1774, 1776, 1778, 1780, 1782, 1784, - 1786, 1788, 1790, 1792, 1794, 1796, 1798, 1800, - 1802, 1804, 1806, 1808, 1810, 1812, 1814, 1816, - 1818, 1820, 1822, 1824, 1826, 1828, 1830, 1832, - 1834, 1836, 1838, 1840, 1842, 1844, 1846, 1848, - 1850, 1852, 1854, 1856, 1858, 1860, 1862, 1864, - 1866, 1868, 1870, 1872, 1874, 1876, 1878, 1880, - 1882, 1884, 1886, 1888, 1890, 1892, 1894, 1896, - 1898, 1900, 1902, 1904, 1906, 1908, 1910, 1912, - 1914, 1916, 1918, 1920, 1922, 1924, 1926, 1928, - 1930, 1932, 1934, 1936, 1938, 1940, 1942, 1944, - 1946, 1948, 1950, 1952, 1954, 1956, 1958, 1960, - 1962, 1964, 1966, 1968, 1970, 1972, 1974, 1976, - 1978, 1980, 1982, 1984, 1986, 1988, 1990, 1992, - 1994, 1996, 1998, 2000, 2002, 2004, 2006, 2008, - 2010, 2012, 2014, 2016, 2018, 2020, 2022, 2024, - 2026, 2028, 2030, 2032, 2034, 2036, 2038, 2040, - 2042, 2044, 2046, 2048, 2050, 2052, 2054, 2056, - 2058, 2060, 2062, 2064, 2066, 2068, 2070, 2072, - 2074, 2076, 2078, 2080, 2082, 2084, 2086, 2088, - 2090, 2092, 2094, 2096, 2098, 2100, 2102, 2104, - 2106, 2108, 2110, 2112, 2114, 2116, 2118, 2120, - 2122, 2124, 2126, 2128, 2130, 2132, 2134, 2136, - 2138, 2140, 2142, 2144, 2146, 2148, 2150, 2152, - 2154, 2159, 2161, 2166, 2168, 2170, 2175, 2177, - 2179, 2181, 2186, 2188, 2190, 2192, 2196, 2202, - 2204, 2209, 2211, 2213, 2215, 2217, 2219, 2221, - 2223, 2225, 2227, 2228, 2229, 2231, 2233, 2234, - 2235, 2236, 2237, 2239, 2241, 2242, 2243, 2244, - 2246, 2248, 2250, 2252, 2254, 2256, 2258, 2260, - 2262, 2264, 2266, 2268, 2270, 2274, 2275, 2276, - 2278, 2282, 2286, 2288, 2292, 2296, 2297, 2298, - 2300, 2302, 2304, 2306, 2311, 2315, 2319, 2321, - 2323, 2325, 2327, 2328, 2330, 2332, 2334, 2336, - 2338, 2340, 2342, 2344, 2346, 2348, 2350, 2352, - 2354, 2356, 2358, 2360, 2362, 2364, 2366, 2368, - 2370, 2372, 2373, 2374, 2376, 2378, 2379, 2380, - 2383, 2386, 2389, 2392, 2394, 2396, 2398, 2400, - 2402, 2404, 2405, 2406, 2407, 2409, 2413, 2415, - 2417, 2423, 2427, 2428, 2429, 2430, 2431, 2432, - 2433, 2434, 2438, 2440, 2442, 2446, 2448, 2450, - 2452, 2454, 2456, 2458, 2460, 2462, 2464, 2466, - 2468, 2470, 2472, 2474, 2475, 2478, 2481, 2486, - 2491, 2494, 2497, 2500, 2503, 2508, 2513, 2516, - 2519, 2521, 2523, 2525, 2527, 2529, 2531, 2533, - 2534, 2536, 2538, 2540, 2542, 2544, 2545, 2546, - 2547, 2551, 2555, 2557, 2561, 2565, 2569, 2573, - 2577, 2579, 2583, 2585, 2587, 2589, 2591, 2593, - 2595, 2597, 2599, 2600, 2602, 2604, 2606, 2608, - 2610, 2612, 2614, 2616, 2617, 2618, 2619, 2621, - 2623, 2625, 2627, 2628, 2629, 2631, 2633, 2635, - 2637, 2639, 2641, 2642, 2644, 2646, 2648, 2650, - 2651, 2652, 2654, 2656, 2658, 2660, 2662, 2664, - 2666, 2668, 2669, 2670, 2672, 2673, 2676, 2679, - 2681, 2684, 2685, 2686, 2688, 2689, 2691, 2693, - 2695, 2697, 2699, 2700, 2701, 2702, 2703, 2704, - 2707, 2712, 2717, 2722, 2727, 2730, 2735, 2740, - 2742, 2744, 2746, 2748, 2749, 2750, 2752, 2754, - 2756, 2758, 2760, 2762, 2764, 2765, 2766, 2767, - 2768, 2769, 2770, 2775, 2780, 2781, 2782, 2783, - 2784, 2785, 2786, 2787, 2788, 2789, 2790, 2791, - 2792, 2793, 2794, 2795, 2796, 2797, 2798, 2799, - 2800, 2801, 2802, 2803, 2804, 2805, 2806, 2807, - 2808, 2809, 2810, 2811, 2812, 2813, 2814, 2815, - 2816, 2817, 2818, 2819, 2820, 2821, 2822, 2823, - 2824, 2825, 2826, 2827, 2828, 2829, 2830, 2831, - 2832, 2833, 2834, 2835, 2836, 2837, 2838, 2839, - 2840, 2841, 2842, 2843, 2844, 2845, 2846, 2847, - 2848, 2849, 2850, 2851, 2852, 2853, 2854, 2855, - 2856, 2857, 2858, 2859, 2860, 2861, 2862, 2863, - 2864, 2865, 2866, 2867, 2868, 2869, 2870, 2871, - 2872, 2873, 2874, 2875, 2876, 2877, 2878, 2879, - 2880, 2881, 2882, 2883, 2884, 2885, 2886, 2887, - 2888, 2889, 2890, 2891, 2892, 2893, 2894, 2895, - 2896, 2897, 2898, 2899, 2900, 2901, 2902, 2903, - 2904, 2905, 2906, 2907, 2908, 2909, 2910, 2911, - 2912, 2913, 2914, 2915, 2916, 2917, 2918, 2919, - 2920, 2921, 2922, 2923, 2924, 2925, 2926, 2927, - 2928, 2929, 2930, 2931, 2932, 2933, 2934, 2935, - 2936, 2937, 2938, 2939, 2940, 2941, 2942, 2943, - 2944, 2945, 2946, 2947, 2948, 2949, 2950, 2951, - 2952, 2953, 2954, 2955, 2956, 2957, 2958, 2959, - 2960, 2961, 2962, 2963, 2964, 2965, 2966, 2967, - 2968, 2969, 2970, 2971, 2972, 2973, 2974, 2975, - 2976, 2977, 2978, 2979, 2980, 2981, 2983, 2985, - 2986, 2987, 2988, 2989, 2990, 2991, 2992, 2993, - 2994, 2995, 2996, 2997, 2998, 2999, 3000, 3001, - 3002, 3003, 3004, 3005, 3006, 3007, 3008, 3009, - 3010, 3011, 3012, 3013, 3015, 3017, 3019, 3021, - 3022, 3023, 3024, 3025, 3026, 3027, 3028, 3029, - 3030, 3031, 3032, 3033, 3034, 3036, 3037, 3038, - 3039, 3041, 3042, 3043, 3044, 3045, 3046, 3047, - 3048, 3049, 3050, 3051, 3052, 3053, 3054, 3055, - 3056, 3057, 3058, 3059, 3060, 3061, 3062, 3063, - 3064, 3065, 3066, 3067, 3068, 3069, 3070, 3071, - 3072, 3073, 3074, 3075, 3076, 3077, 3078, 3079, - 3080, 3081, 3082, 3084, 3086, 3087, 3088, 3090, - 3091, 3093, 3095, 3096, 3097, 3099, 3101, 3103, - 3105, 3106, 3107, 3108, 3109, 3110, 3111, 3112, - 3113, 3114, 3115, 3116, 3117, 3118, 3119, 3120, - 3121, 3124, 3127, 3128, 3129, 3130, 3131, 3132, - 3133, 3135, 3137, 3139, 3140, 3141, 3142, 3143, - 3144, 3145, 3147, 3148, 3149, 3150, 3151, 3152, - 3153, 3154, 3155, 3156, 3157, 3158, 3159, 3160, - 3161, 3162, 3163, 3164, 3165, 3166, 3167, 3170, - 3173, 3174, 3175, 3176, 3177, 3178, 3179, 3180, - 3181, 3182, 3183, 3184, 3185, 3186, 3187, 3188, - 3189, 3190, 3191, 3192, 3193, 3194, 3195, 3196, - 3197, 3198, 3199, 3200, 3201, 3202, 3203, 3204, - 3205, 3206, 3207, 3208, 3209, 3210, 3211, 3212, - 3213, 3214, 3215, 3216, 3217, 3218, 3219, 3220, - 3221, 3222, 3223, 3224, 3225, 3226, 3227, 3230, - 3232, 3235, 3238, 3240, 3243, 3246, 3249, 3252, - 3253, 3256, 3257, 3258, 3259, 3260, 3261, 3265, - 3267, 3270, 3271, 3272, 3273, 3274, 3275, 3276, - 3277, 3278, 3279, 3280, 3281, 3282, 3283, 3284, - 3285, 3286, 3287, 3288, 3289, 3290, 3291, 3292, - 3293, 3294, 3295, 3296, 3297, 3298, 3299, 3300, - 3301, 3302, 3303, 3304, 3305, 3306, 3307, 3308, - 3309, 3310, 3311, 3312, 3313, 3314, 3315, 3316, - 3317, 3318, 3319, 3320, 3321, 3322, 3323, 3324, - 3325, 3327, 3328, 3329, 3330, 3331, 3332, 3333, - 3334, 3335, 3336, 3337, 3338, 3339, 3340, 3341, - 3342, 3343, 3344, 3345, 3346, 3347, 3348, 3349, - 3350, 3351, 3352, 3353, 3354, 3355, 3356, 3357, - 3358, 3359, 3360, 3361, 3362, 3363, 3364, 3365, - 3366, 3369, 3372, 3375, 3378, 3381, 3384, 3387, - 3390, 3393, 3396, 3399, 3402, 3405, 3408, 3411, - 3412, 3413, 3414, 3415, 3417, 3418, 3419, 3420, - 3421, 3422, 3423, 3424, 3425, 3426, 3427, 3428, - 3429, 3430, 3431, 3432, 3433, 3434, 3435, 3436, - 3437, 3438, 3439, 3440, 3441, 3442, 3443, 3444, - 3445, 3446, 3447, 3448, 3449, 3450, 3451, 3452, - 3453, 3454, 3455, 3456, 3457, 3458, 3459, 3460, - 3461, 3462, 3463, 3464, 3465, 3466, 3467, 3468, - 3469, 3470, 3471, 3472, 3473, 3474, 3475, 3476, - 3477, 3478, 3481, 3484, 3485, 3486, 3487, 3488, - 3489, 3490, 3491, 3492, 3493, 3494, 3495, 3496, - 3497, 3498, 3499, 3500, 3501, 3502, 3503, 3504, - 3505, 3506, 3507, 3508, 3509, 3510, 3511, 3512, - 3513, 3514, 3515, 3516, 3517, 3518, 3519, 3520, - 3521, 3522, 3523, 3524, 3525, 3526, 3527, 3528, - 3529, 3530, 3531, 3532, 3533, 3534, 3535, 3536, - 3537, 3538, 3539, 3540, 3541, 3542, 3543, 3544, - 3545, 3546, 3549, 3552, 3555, 3556, 3557, 3558, - 3559, 3560, 3561, 3562, 3563, 3564, 3565, 3566, - 3567, 3568, 3569, 3570, 3571, 3574, 3577, 3578, - 3579, 3582, 3583, 3584, 3585, 3586, 3589, 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3999, 4000, 4001, 4002, 4003, 4004, 4005, + 4006, 4007, 4008, 4009, 4010, 4011, 4012, 4013, + 4014, 4015, 4016, 4017, 4018, 4019, 4020, 4021, + 4022, 4023, 4024, 4025, 4026, 4027, 4028, 4029, + 4030, 4031, 4032, 4033, 4034, 4035, 4036, 4037, + 4038, 4040, 4042, 4044, 4046, 4048, 4049, 4050, + 4053, 4056, 4057, 4058, 4059, 4060 }; /* i386 mnemonics table. */ |