November 7th 2017 Toolchain Release

It's been about two months since the last stable toolchain release, so
we're a bit past due for a new one.  Here's a summary of the changes
in this release

* binutils-gdb is still based on the 2.29 upstream release, with the
following patches:
    * d0176cb1653b ("RISC-V: Fix riscv g++ testsuite EH failures.")
    * d5feabfac32f ("RISC-V: Add satp as an alias for sptbr")
    * 2f9782d95416 ("(WIP SIM): Fix jal and jalr")
    * f64577d1c916 ("RISC-V: Fix disassembly of c.addi4spn, c.addi16sp, c.lui when imm=0")
    * d51d92c4d06b ("RISC-V: Only relax to C.LUI when imm != 0 and rd != 0/2")
    * 3593f7f30f80 ("Fix my previous gas/ChangeLog entry")
    * 164a62116dc9 ("RISC-V: Don't emit 2-byte NOPs if the C extension is disabled")
    * 915b00e356e0 ("RISC-V: Relax RISCV_PCREL_* to RISCV_GPREL_*")
    * fa753df2d560 ("RISC-V: Add R_RISCV_DELETE, which marks bytes for deletion")
    * 9eb250cb914c ("RISC-V: Mark unsupported gas testcases")
    * 0d96fbb3095f ("riscv: Cache the max alignment of output sections")
    * 60cda8de81dc ("RISC-V: Avoid emitting invalid instructions in mixed RVC/no-RVC code")
    * 296c682e9d92 ("RISC-V: Print an error when unable to align a section")
    * 1bfb4ecbd84c ("RISC-V: Support PCREL_* relocations agaist weak undefined symbols")
    * d3fae8db583d ("Improve handling of ADD and SUB relocations on the RISCV target.")
    * 404de0666a6a ("RISC-V: Mark "c.nop" as an alias")
    * dfbf9e44a0e1 ("Fix problems parsing RISCV architecture extenstions in the assembler.")
    * 697d5b8ee280 ("(RISC-V GDB) Only save FPRs on harts that support F/D/Q")
    * 495d737e62c0 ("(RISC-V GDB) GDB update")
    * c950de297cd7 ("(RISC-V GDB) RISC-V GDB Port")
    * dd9a28c0966d ("Bump version to 2.29")
* GCC is now based on the 7.2.0 upstream release, with the following
patches
    * b731149757b9 ("RISC-V: Implement movmemsi")
    * 605bc7b5e06a ("RISC-V: Define MUSL_DYNAMIC_LINKER")
    * 2423096b0696 ("RISC-V: Emit "i" suffix for instructions with immediate operands")
    * 327d99b09bc0 ("RISC-V: If -m[no-]strict-align is not passed, assume its value from -mtune")
    * f34a83e82258 ("RISC-V: Set SLOW_BYTE_ACCESS=1")
    * 7dde69e2c5f7 ("RISC-V: Handle non-legitimate address in riscv_legitimize_move")
    * 1751fbe7b9e8 ("RISC-V: Use "@minus{}2 GB" instead of "-2 GB" in invoke.texi")
    * 6d1f1f891869 ("RISC-V: Document the medlow and medany code models")
    * d2d1f783b2c1 ("RISC-V: Correct and improve the "-mabi" documentation")
    * d13dd0242604 ("RISC-V: Add Sign/Zero extend patterns for PIC loads")
    * 341375637a7d ("RISC-V: Add -mstrict-align option")
    * f47f9c2b3b90 ("RISC-V: Unify indention in riscv.md")
    * 1bd23ca8c30f ("Update ChangeLog and version files for release")
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