From b5d67b3f53ed7392a86110ebe4bfd7dcdda65ddd Mon Sep 17 00:00:00 2001
From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Wed, 22 Jul 2015 13:03:22 -0700
Subject: Avoid t0 for indirect calls

We sometimes use t0 as a link register, e.g. for the compressed prologues
and epilogues, and so we want microarchitectures to push the RAS when
rd=t0 and pop the RAS when rs1=t0.  Thus, we want to avoid using t0 for
indirect calls to avoid errant RAS operations.
---
 gcc/gcc/config/riscv/constraints.md |  3 +++
 gcc/gcc/config/riscv/riscv.h        |  5 ++++-
 gcc/gcc/config/riscv/riscv.md       | 10 +++++-----
 3 files changed, 12 insertions(+), 6 deletions(-)

(limited to 'gcc')

diff --git a/gcc/gcc/config/riscv/constraints.md b/gcc/gcc/config/riscv/constraints.md
index a348fd1..19dbbd7 100644
--- a/gcc/gcc/config/riscv/constraints.md
+++ b/gcc/gcc/config/riscv/constraints.md
@@ -30,6 +30,9 @@
 (define_register_constraint "j" "T_REGS"
   "@internal")
 
+(define_register_constraint "l" "JALR_REGS"
+  "@internal")
+
 ;; Integer constraints
 
 (define_constraint "Z"
diff --git a/gcc/gcc/config/riscv/riscv.h b/gcc/gcc/config/riscv/riscv.h
index bbfec02..f4d432c 100644
--- a/gcc/gcc/config/riscv/riscv.h
+++ b/gcc/gcc/config/riscv/riscv.h
@@ -549,6 +549,7 @@ enum reg_class
 {
   NO_REGS,			/* no registers in set */
   T_REGS,			/* registers used by indirect sibcalls */
+  JALR_REGS,			/* registers used by indirect calls */
   GR_REGS,			/* integer registers */
   FP_REGS,			/* floating point registers */
   FRAME_REGS,			/* $arg and $frame */
@@ -568,6 +569,7 @@ enum reg_class
 {									\
   "NO_REGS",								\
   "T_REGS",								\
+  "JALR_REGS",								\
   "GR_REGS",								\
   "FP_REGS",								\
   "FRAME_REGS",								\
@@ -588,7 +590,8 @@ enum reg_class
 #define REG_CLASS_CONTENTS									\
 {												\
   { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
-  { 0xf00000e0, 0x00000000, 0x00000000 },	/* T_REGS */		\
+  { 0xf0000040, 0x00000000, 0x00000000 },	/* T_REGS */		\
+  { 0xffffff40, 0x00000000, 0x00000000 },	/* JALR_REGS */		\
   { 0xffffffff, 0x00000000, 0x00000000 },	/* GR_REGS */		\
   { 0x00000000, 0xffffffff, 0x00000000 },	/* FP_REGS */		\
   { 0x00000000, 0x00000000, 0x00000003 },	/* FRAME_REGS */	\
diff --git a/gcc/gcc/config/riscv/riscv.md b/gcc/gcc/config/riscv/riscv.md
index 8ce17ab..af3a3c2 100644
--- a/gcc/gcc/config/riscv/riscv.md
+++ b/gcc/gcc/config/riscv/riscv.md
@@ -2122,7 +2122,7 @@
 })
 
 (define_insn "indirect_jump<mode>"
-  [(set (pc) (match_operand:P 0 "register_operand" "r"))]
+  [(set (pc) (match_operand:P 0 "register_operand" "l"))]
   ""
   "jr\t%0"
   [(set_attr "type" "jump")
@@ -2146,7 +2146,7 @@
 })
 
 (define_insn "tablejump<mode>"
-  [(set (pc) (match_operand:GPR 0 "register_operand" "r"))
+  [(set (pc) (match_operand:GPR 0 "register_operand" "l"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "jr\t%0"
@@ -2343,7 +2343,7 @@
 })
 
 (define_insn "call_internal"
-  [(call (mem:SI (match_operand 0 "call_insn_operand" "r,S"))
+  [(call (mem:SI (match_operand 0 "call_insn_operand" "l,S"))
 	 (match_operand 1 "" ""))
    (clobber (reg:SI RETURN_ADDR_REGNUM))]
   ""
@@ -2366,7 +2366,7 @@
 ;; See comment for call_internal.
 (define_insn "call_value_internal"
   [(set (match_operand 0 "register_operand" "")
-        (call (mem:SI (match_operand 1 "call_insn_operand" "r,S"))
+        (call (mem:SI (match_operand 1 "call_insn_operand" "l,S"))
               (match_operand 2 "" "")))
    (clobber (reg:SI RETURN_ADDR_REGNUM))]
   ""
@@ -2378,7 +2378,7 @@
 ;; See comment for call_internal.
 (define_insn "call_value_multiple_internal"
   [(set (match_operand 0 "register_operand" "")
-        (call (mem:SI (match_operand 1 "call_insn_operand" "r,S"))
+        (call (mem:SI (match_operand 1 "call_insn_operand" "l,S"))
               (match_operand 2 "" "")))
    (set (match_operand 3 "register_operand" "")
 	(call (mem:SI (match_dup 1))
-- 
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