From 27cbd8e17ce719a0be205ea8187e155accca94fe Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 18 Sep 2015 23:34:47 -0700 Subject: binutils: bfd: move RVC fields to the right place --- binutils/include/opcode/riscv.h | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) (limited to 'binutils') diff --git a/binutils/include/opcode/riscv.h b/binutils/include/opcode/riscv.h index 1a01f25..02a676c 100644 --- a/binutils/include/opcode/riscv.h +++ b/binutils/include/opcode/riscv.h @@ -26,20 +26,6 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #include #include -/* RVC fields. */ - -#define OP_MASK_CRS2 0x1f -#define OP_SH_CRS2 2 -#define OP_MASK_CRS1S 0x7 -#define OP_SH_CRS1S 7 -#define OP_MASK_CRS2S 0x7 -#define OP_SH_CRS2S 2 - -static const char rvc_rs1_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 7 }; -#define rvc_rd_regmap rvc_rs1_regmap -#define rvc_rs2b_regmap rvc_rs1_regmap -static const char rvc_rs2_regmap[8] = { 20, 21, 2, 3, 4, 5, 6, 0 }; - typedef uint64_t insn_t; static inline unsigned int riscv_insn_length (insn_t insn) @@ -239,6 +225,17 @@ static const char * const riscv_pred_succ[16] = { #define OP_MASK_CSR 0xfff #define OP_SH_CSR 20 +/* RVC fields. */ + +#define OP_MASK_CRS2 0x1f +#define OP_SH_CRS2 2 +#define OP_MASK_CRS1S 0x7 +#define OP_SH_CRS1S 7 +#define OP_MASK_CRS2S 0x7 +#define OP_SH_CRS2S 2 + +/* ABI names for selected x-registers. */ + #define X_RA 1 #define X_SP 2 #define X_GP 3 -- cgit v1.1