From d00938ea9eac83f082a6688d3040e23f00867b53 Mon Sep 17 00:00:00 2001
From: Kito Cheng <kito.cheng@sifive.com>
Date: Mon, 29 Mar 2021 17:09:19 +0800
Subject: Bump gcc and binutils

 - Update to RVV 0.10
 - Implement explicitly VL API.
---
 riscv-binutils | 2 +-
 riscv-gcc      | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/riscv-binutils b/riscv-binutils
index 90b9b49..484ebca 160000
--- a/riscv-binutils
+++ b/riscv-binutils
@@ -1 +1 @@
-Subproject commit 90b9b492b559fd72423896feccab526e2528fc66
+Subproject commit 484ebca6d63ab52301a77a8886c98f570eaa4157
diff --git a/riscv-gcc b/riscv-gcc
index dc7e524..66a2be8 160000
--- a/riscv-gcc
+++ b/riscv-gcc
@@ -1 +1 @@
-Subproject commit dc7e524c23a579120d94912802a6ba174b3a7ed6
+Subproject commit 66a2be891b672cdb3088d44a7c50939675f8302d
-- 
cgit v1.1