From 9e43ec4eafc7a96b9aa19397ffbc9dbeb161efb2 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 21 Mar 2017 15:50:13 -0700
Subject: Set up PMP if present

---
 encoding.h     | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++--
 p/riscv_test.h |  9 ++++++---
 v/vm.c         | 14 ++++++++++++--
 3 files changed, 71 insertions(+), 7 deletions(-)

diff --git a/encoding.h b/encoding.h
index 0af9132..4f0d0a4 100644
--- a/encoding.h
+++ b/encoding.h
@@ -17,7 +17,7 @@
 #define MSTATUS_FS          0x00006000
 #define MSTATUS_XS          0x00018000
 #define MSTATUS_MPRV        0x00020000
-#define MSTATUS_PUM         0x00040000
+#define MSTATUS_SUM         0x00040000
 #define MSTATUS_MXR         0x00080000
 #define MSTATUS_TVM         0x00100000
 #define MSTATUS_TW          0x00200000
@@ -32,7 +32,8 @@
 #define SSTATUS_SPP         0x00000100
 #define SSTATUS_FS          0x00006000
 #define SSTATUS_XS          0x00018000
-#define SSTATUS_PUM         0x00040000
+#define SSTATUS_SUM         0x00040000
+#define SSTATUS_MXR         0x00080000
 #define SSTATUS32_SD        0x80000000
 #define SSTATUS64_SD        0x8000000000000000
 
@@ -123,6 +124,16 @@
 #define SPTBR_MODE_SV57 10
 #define SPTBR_MODE_SV64 11
 
+#define PMP_R     0x01
+#define PMP_W     0x02
+#define PMP_X     0x04
+#define PMP_M     0x08
+#define PMP_NAPOT 0x10
+#define PMP_TOR   0x20
+#define PMP_EN    0x40
+#define PMP_LOCK  0x80
+#define PMP_SHIFT 2
+
 #define IRQ_S_SOFT   1
 #define IRQ_H_SOFT   2
 #define IRQ_M_SOFT   3
@@ -793,6 +804,26 @@
 #define CSR_MCAUSE 0x342
 #define CSR_MBADADDR 0x343
 #define CSR_MIP 0x344
+#define CSR_PMPCFG0 0x3a0
+#define CSR_PMPCFG1 0x3a1
+#define CSR_PMPCFG2 0x3a2
+#define CSR_PMPCFG3 0x3a3
+#define CSR_PMPADDR0 0x3b0
+#define CSR_PMPADDR1 0x3b1
+#define CSR_PMPADDR2 0x3b2
+#define CSR_PMPADDR3 0x3b3
+#define CSR_PMPADDR4 0x3b4
+#define CSR_PMPADDR5 0x3b5
+#define CSR_PMPADDR6 0x3b6
+#define CSR_PMPADDR7 0x3b7
+#define CSR_PMPADDR8 0x3b8
+#define CSR_PMPADDR9 0x3b9
+#define CSR_PMPADDR10 0x3ba
+#define CSR_PMPADDR11 0x3bb
+#define CSR_PMPADDR12 0x3bc
+#define CSR_PMPADDR13 0x3bd
+#define CSR_PMPADDR14 0x3be
+#define CSR_PMPADDR15 0x3bf
 #define CSR_TSELECT 0x7a0
 #define CSR_TDATA1 0x7a1
 #define CSR_TDATA2 0x7a2
@@ -1263,6 +1294,26 @@ DECLARE_CSR(mepc, CSR_MEPC)
 DECLARE_CSR(mcause, CSR_MCAUSE)
 DECLARE_CSR(mbadaddr, CSR_MBADADDR)
 DECLARE_CSR(mip, CSR_MIP)
+DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
+DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
+DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
+DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
+DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
+DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
+DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
+DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
+DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
+DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
+DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
+DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
+DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
+DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
+DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
+DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
+DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
+DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
+DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
+DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
 DECLARE_CSR(tselect, CSR_TSELECT)
 DECLARE_CSR(tdata1, CSR_TDATA1)
 DECLARE_CSR(tdata2, CSR_TDATA2)
diff --git a/p/riscv_test.h b/p/riscv_test.h
index 9f17ae5..fe71eae 100644
--- a/p/riscv_test.h
+++ b/p/riscv_test.h
@@ -54,10 +54,13 @@
 #endif
 
 #define INIT_SPTBR                                                      \
-  csrr a0, misa;                                                        \
-  slli a0, a0, (__riscv_xlen - 1) - ('S' - 'A');                        \
-  bgez a0, 1f;                                                          \
+  la t0, 1f;                                                            \
+  csrw mtvec, t0;                                                       \
   csrwi sptbr, 0;                                                       \
+  li t0, -1;        /* Set up a PMP to permit all accesses */           \
+  csrw CSR_PMPADDR0, t0;                                                \
+  li t0, PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X;            \
+  csrw CSR_PMPCFG0, t0;                                                 \
 1:
 
 #define RVTEST_ENABLE_SUPERVISOR                                        \
diff --git a/v/vm.c b/v/vm.c
index 2e057fb..bdbab6a 100644
--- a/v/vm.c
+++ b/v/vm.c
@@ -228,6 +228,16 @@ void vm_boot(uintptr_t test_addr)
   write_csr(sptbr, ((uintptr_t)l1pt >> PGSHIFT) |
                    (vm_choice * (SPTBR_MODE & ~(SPTBR_MODE<<1))));
 
+  // Set up PMPs if present, ignoring illegal instruction trap if not.
+  uintptr_t pmpc = PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X;
+  asm volatile ("la t0, 1f\n\t"
+                "csrw mtvec, t0\n\t"
+                "csrw %2, %3\n\t"
+                "csrw %0, %1\n\t"
+                "1:"
+                :: "i" (CSR_PMPCFG0), "r" (pmpc), "i" (CSR_PMPADDR0), "r" (-1)
+                : "t0");
+
   // set up supervisor trap handling
   write_csr(stvec, pa2kva(trap_entry));
   write_csr(sscratch, pa2kva(read_csr(mscratch)));
@@ -236,8 +246,8 @@ void vm_boot(uintptr_t test_addr)
     (1 << CAUSE_FAULT_FETCH) |
     (1 << CAUSE_FAULT_LOAD) |
     (1 << CAUSE_FAULT_STORE));
-  // FPU on; accelerator on
-  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS);
+  // FPU on; accelerator on; allow supervisor access to user memory access
+  write_csr(mstatus, MSTATUS_FS | MSTATUS_XS | MSTATUS_SUM);
   write_csr(mie, 0);
 
   random = 1 + (random % MAX_TEST_PAGES);
-- 
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