From 3d45ca302dbf5ac22cfac8fb025c05c735c35e26 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sat, 30 Apr 2016 20:44:46 -0700 Subject: ERET -> xRET; change memory map --- encoding.h | 38 ++++++++++++++++++++++---------------- p/link.ld | 2 +- p/riscv_test.h | 28 ++++++++++++++++------------ pt/riscv_test.h | 2 +- v/entry.S | 6 ++++-- v/vm.c | 15 ++++++++------- 6 files changed, 52 insertions(+), 39 deletions(-) diff --git a/encoding.h b/encoding.h index c57804d..5cb7ff5 100644 --- a/encoding.h +++ b/encoding.h @@ -67,9 +67,12 @@ #define IRQ_COP 12 #define IRQ_HOST 13 -#define DEFAULT_RSTVEC 0x0 -#define DEFAULT_NMIVEC 0x4 -#define DEFAULT_MTVEC 0x8 +#define DEFAULT_RSTVEC 0x00001000 +#define DEFAULT_NMIVEC 0x00001004 +#define DEFAULT_MTVEC 0x00001010 +#define CONFIG_STRING_ADDR 0x0000100C +#define EXT_IO_BASE 0x40000000 +#define DRAM_BASE 0x80000000 // page table entry (PTE) fields #define PTE_V 0x001 // Valid @@ -345,12 +348,18 @@ #define MASK_LR_D 0xf9f0707f #define MATCH_SC_D 0x1800302f #define MASK_SC_D 0xf800707f -#define MATCH_SCALL 0x73 -#define MASK_SCALL 0xffffffff -#define MATCH_SBREAK 0x100073 -#define MASK_SBREAK 0xffffffff +#define MATCH_ECALL 0x73 +#define MASK_ECALL 0xffffffff +#define MATCH_EBREAK 0x100073 +#define MASK_EBREAK 0xffffffff +#define MATCH_URET 0x200073 +#define MASK_URET 0xffffffff #define MATCH_SRET 0x10200073 #define MASK_SRET 0xffffffff +#define MATCH_HRET 0x20200073 +#define MASK_HRET 0xffffffff +#define MATCH_MRET 0x30200073 +#define MASK_MRET 0xffffffff #define MATCH_SFENCE_VM 0x10400073 #define MASK_SFENCE_VM 0xfff07fff #define MATCH_WFI 0x10500073 @@ -647,7 +656,6 @@ #define CSR_MIDELEG 0x303 #define CSR_MIE 0x304 #define CSR_MTVEC 0x305 -#define CSR_MTIMECMP 0x321 #define CSR_MSCRATCH 0x340 #define CSR_MEPC 0x341 #define CSR_MCAUSE 0x342 @@ -669,15 +677,13 @@ #define CSR_MVENDORID 0xf11 #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 -#define CSR_MCFGADDR 0xf14 -#define CSR_MHARTID 0xf15 +#define CSR_MHARTID 0xf14 #define CSR_MTOHOST 0x7c0 #define CSR_MFROMHOST 0x7c1 #define CSR_MRESET 0x7c2 #define CSR_CYCLEH 0xc80 #define CSR_TIMEH 0xc81 #define CSR_INSTRETH 0xc82 -#define CSR_MTIMECMPH 0x361 #define CSR_MUCYCLE_DELTAH 0x780 #define CSR_MUTIME_DELTAH 0x781 #define CSR_MUINSTRET_DELTAH 0x782 @@ -787,9 +793,12 @@ DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(scall, MATCH_SCALL, MASK_SCALL) -DECLARE_INSN(sbreak, MATCH_SBREAK, MASK_SBREAK) +DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) +DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) +DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) +DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) +DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) @@ -952,7 +961,6 @@ DECLARE_CSR(medeleg, CSR_MEDELEG) DECLARE_CSR(mideleg, CSR_MIDELEG) DECLARE_CSR(mie, CSR_MIE) DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mtimecmp, CSR_MTIMECMP) DECLARE_CSR(mscratch, CSR_MSCRATCH) DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) @@ -974,7 +982,6 @@ DECLARE_CSR(misa, CSR_MISA) DECLARE_CSR(mvendorid, CSR_MVENDORID) DECLARE_CSR(marchid, CSR_MARCHID) DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mcfgaddr, CSR_MCFGADDR) DECLARE_CSR(mhartid, CSR_MHARTID) DECLARE_CSR(mtohost, CSR_MTOHOST) DECLARE_CSR(mfromhost, CSR_MFROMHOST) @@ -982,7 +989,6 @@ DECLARE_CSR(mreset, CSR_MRESET) DECLARE_CSR(cycleh, CSR_CYCLEH) DECLARE_CSR(timeh, CSR_TIMEH) DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(mtimecmph, CSR_MTIMECMPH) DECLARE_CSR(mucycle_deltah, CSR_MUCYCLE_DELTAH) DECLARE_CSR(mutime_deltah, CSR_MUTIME_DELTAH) DECLARE_CSR(muinstret_deltah, CSR_MUINSTRET_DELTAH) diff --git a/p/link.ld b/p/link.ld index eeb3730..525fe34 100644 --- a/p/link.ld +++ b/p/link.ld @@ -2,7 +2,7 @@ OUTPUT_ARCH( "riscv" ) SECTIONS { - . = 0; + . = 0x80000000; .text.init : { *(.text.init) } .text : { *(.text) } .data ALIGN(0x1000) : { *(.data) } diff --git a/p/riscv_test.h b/p/riscv_test.h index cdc256e..903f23f 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -91,18 +91,21 @@ _start: \ /* reset vector */ \ j reset_vector; \ - /* NMI vector */ \ - j other_exception; \ - /* trap vector */ \ +trap_vector: \ /* test whether the test came from pass/fail */ \ - la t5, ecall; \ - csrr t6, mepc; \ + csrr t5, mcause; \ + li t6, CAUSE_USER_ECALL; \ + beq t5, t6, write_tohost; \ + li t6, CAUSE_SUPERVISOR_ECALL; \ + beq t5, t6, write_tohost; \ + li t6, CAUSE_MACHINE_ECALL; \ beq t5, t6, write_tohost; \ /* if an mtvec_handler is defined, jump to it */ \ la t5, mtvec_handler; \ - bnez t5, mtvec_handler; \ + beqz t5, 1f; \ + jr t5; \ /* was it an interrupt or an exception? */ \ - csrr t5, mcause; \ + 1: csrr t5, mcause; \ bgez t5, handle_exception; \ INTERRUPT_HANDLER; \ handle_exception: \ @@ -117,6 +120,8 @@ reset_vector: \ RISCV_MULTICORE_DISABLE; \ CHECK_XLEN; \ li TESTNUM, 0; \ + la t0, trap_vector; \ + csrw mtvec, t0; \ /* if an stvec_handler is defined, delegate exceptions to it */ \ la t0, stvec_handler; \ beqz t0, 1f; \ @@ -137,7 +142,7 @@ reset_vector: \ la t0, 1f; \ csrw mepc, t0; \ csrr a0, mhartid; \ - eret; \ + mret; \ 1: //----------------------------------------------------------------------- @@ -145,8 +150,7 @@ reset_vector: \ //----------------------------------------------------------------------- #define RVTEST_CODE_END \ -ecall: ecall; \ - j ecall + unimp //----------------------------------------------------------------------- // Pass/Fail Macro @@ -155,7 +159,7 @@ ecall: ecall; \ #define RVTEST_PASS \ fence; \ li TESTNUM, 1; \ - j ecall + ecall #define TESTNUM x28 #define RVTEST_FAIL \ @@ -163,7 +167,7 @@ ecall: ecall; \ 1: beqz TESTNUM, 1b; \ sll TESTNUM, TESTNUM, 1; \ or TESTNUM, TESTNUM, 1; \ - j ecall + ecall //----------------------------------------------------------------------- // Data Section Macro diff --git a/pt/riscv_test.h b/pt/riscv_test.h index 7100a20..34c2a33 100644 --- a/pt/riscv_test.h +++ b/pt/riscv_test.h @@ -29,7 +29,7 @@ csrr t5, mtime; \ addi t5, t5, TIMER_INTERVAL; \ csrw mtimecmp, t5; \ - eret; \ + mret; \ //----------------------------------------------------------------------- // Data Section Macro diff --git a/v/entry.S b/v/entry.S index f503764..64d9606 100644 --- a/v/entry.S +++ b/v/entry.S @@ -32,6 +32,8 @@ trap_vector: j wtf handle_reset: + la t0, trap_vector + csrw mtvec, t0 la sp, STACK_TOP - SIZEOF_TRAPFRAME_T csrw mscratch, sp li a1, 1337 @@ -73,7 +75,7 @@ pop_tf: LOAD x30,30*REGBYTES(a0) LOAD x31,31*REGBYTES(a0) LOAD a0,10*REGBYTES(a0) - eret + sret .global trap_entry trap_entry: @@ -142,7 +144,7 @@ handle_tohost: csrr t0, mepc addi t0, t0, 4 csrw mepc, t0 - eret + mret wtf: li a0, 841 diff --git a/v/vm.c b/v/vm.c index 2851d38..ef1f733 100644 --- a/v/vm.c +++ b/v/vm.c @@ -10,7 +10,8 @@ void trap_entry(); void pop_tf(trapframe_t*); void do_tohost(long tohost_value); -#define pa2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) +#define pa2kva(pa) ((void*)(pa) - DRAM_BASE - MEGAPAGE_SIZE) +#define uva2kva(pa) ((void*)(pa) - MEGAPAGE_SIZE) static uint64_t lfsr63(uint64_t x) { @@ -82,9 +83,9 @@ void evict(unsigned long addr) { // check referenced and dirty bits assert(user_l3pt[addr/PGSIZE] & PTE_R); - if (memcmp((void*)addr, pa2kva(addr), PGSIZE)) { + if (memcmp((void*)addr, uva2kva(addr), PGSIZE)) { assert(user_l3pt[addr/PGSIZE] & PTE_D); - memcpy((void*)addr, pa2kva(addr), PGSIZE); + memcpy((void*)addr, uva2kva(addr), PGSIZE); } user_mapping[addr/PGSIZE].addr = 0; @@ -115,7 +116,7 @@ void handle_fault(unsigned long addr) assert(user_mapping[addr/PGSIZE].addr == 0); user_mapping[addr/PGSIZE] = *node; - memcpy((void*)addr, pa2kva(addr), PGSIZE); + memcpy((void*)addr, uva2kva(addr), PGSIZE); __builtin___clear_cache(0,0); } @@ -208,16 +209,16 @@ void vm_boot(long test_addr, long seed) freelist_tail = pa2kva(&freelist_nodes[MAX_TEST_PAGES-1]); for (long i = 0; i < MAX_TEST_PAGES; i++) { - freelist_nodes[i].addr = (MAX_TEST_PAGES + seed)*PGSIZE; + freelist_nodes[i].addr = DRAM_BASE + (MAX_TEST_PAGES + seed)*PGSIZE; freelist_nodes[i].next = pa2kva(&freelist_nodes[i+1]); seed = LFSR_NEXT(seed); - kernel_l3pt[i] = (i << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_SRWX; + kernel_l3pt[i] = ((i + DRAM_BASE/RISCV_PGSIZE) << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_SRWX; } freelist_nodes[MAX_TEST_PAGES-1].next = 0; trapframe_t tf; memset(&tf, 0, sizeof(tf)); - write_csr(mepc, test_addr); + tf.epc = test_addr - DRAM_BASE; pop_tf(&tf); } -- cgit v1.1