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2021-07-18Fix __clear_cache(0, 0) compilation issue (#30)Daniel Lustig1-1/+1
See also https://github.com/riscv/riscv-pk/pull/240
2020-11-23Merge pull request #27 from bucaps/satp_stval-fixesAndrew Waterman3-5/+5
Minor clang-related fixes
2020-11-24v/entry.S: replace sbadaddr with stvalGokturk Yuksek1-1/+1
The RISC-V Privileged ISA v1.10 uses stval instead of sbadaddr. Although GCC can cope with sbadaddr, clang cannot. It fails with: error: operand must be a valid system register name or an integer in the range [0, 4095]
2020-11-24Replace sptbr with satp throughoutGokturk Yuksek2-4/+4
The RISC-V Privileged ISA v1.10 uses satp instead of sptbr. Although GCC can cope with sptbr, clang cannot. It fails with: error: operand must be a valid system register name or an integer in the range [0, 4095] Modified the variable name in vm.c as well to ensure consistency and avoid possible confusion.
2020-10-14Merge pull request #26 from SandeepRajendran/masterAndrew Waterman1-1/+1
Unconditionally clear mie register while disabling interrupts.
2020-10-14unconditionally clear mie registerSandeep Rajendran1-1/+1
2020-07-14Merge pull request #24 from wuzhy/masterAndrew Waterman1-2/+2
fix a building error
2020-07-14fix a building errorZhi Yong Wu1-2/+2
riscv64-unknown-elf-gcc -march=rv32g -mabi=ilp32 -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -DENTROPY=0xf7930f7 -std=gnu99 -O2 -I/data/riscv/riscv-tools/riscv-tests/isa/../env/v -I/data/riscv/riscv-tools/riscv-tests/isa/macros/scalar -T/data/riscv/riscv-tools/riscv-tests/isa/../env/v/link.ld /data/riscv/riscv-tools/riscv-tests/isa/../env/v/entry.S /data/riscv/riscv-tools/riscv-tests/isa/../env/v/*.c rv32ui/simple.S -o rv32ui-v-simple /opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `tohost': (.tohost+0x0): multiple definition of `tohost'; /tmp/ccOTKaAa.o:(.sbss+0x10): first defined here /opt/riscv/lib/gcc/riscv64-unknown-elf/10.1.0/../../../../riscv64-unknown-elf/bin/ld: /tmp/cc8oFAkO.o: in function `fromhost': (.tohost+0x40): multiple definition of `fromhost'; /tmp/ccOTKaAa.o:(.sbss+0x8): first defined here collect2: error: ld returned 1 exit status /data/riscv/riscv-tools/riscv-tests/isa/Makefile:74: recipe for target 'rv32ui-v-simple' failed make[1]: *** [rv32ui-v-simple] Error 1 make[1]: Leaving directory '/data/riscv/riscv-tools/riscv-tests/isa' Makefile:28: recipe for target 'isa' failed make: *** [isa] Error 2 Signed-off-by: Zhi Yong Wu <zhiyong.wu@sophgo.com>
2020-04-14Merge pull request #23 from chihminchao/rvv-0.9Andrew Waterman3-262/+391
Rvv 0.9
2020-04-14encoding: add new vector instruction in spec 0.9Chih-Min Chao1-0/+27
1. add rtz rounding instructions 2. add vfslide instructions Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14encoding: add new VCSR for vector 0.9Chih-Min Chao3-2/+7
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14encoding: update csr definitionChih-Min Chao1-2/+30
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-04-14encoding: use unified ordering to avoid library changeChih-Min Chao1-258/+327
Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2020-03-05enable vector unit in V environment (#20)Han-Kuan Chen1-0/+3
2020-03-04Initialize x registers in p, pm, pt rather than just v (#21)Andrew Waterman1-1/+35
2020-03-02restore mtvec (#19)Han-Kuan Chen1-1/+1
2020-02-27Enable vector unit in V environment by defaultAndrew Waterman1-2/+2
2020-02-27Update encoding.hAndrew Waterman1-15/+1244
2020-02-24Fix #17 (#18)Paul Donahue1-2/+0
Don't make assumptions about delegatability in medeleg.
2019-12-16Initialize all the x-registers for determinismAndrew Waterman1-0/+32
This isn't required for correctness, but it helps debugging (and, in a few restricted scenarios, it avoids x-prop issues). Closes #16
2019-12-02Merge pull request #15 from chihminchao/ecall_and_vectorAndrew Waterman2-0/+22
Ecall and vector
2019-11-28rvv: add mstatus.vs definition and initial mcaroChih-Min Chao2-0/+18
1. mstatus.vs is similar to mstatus.fs but desiged for vector extension. 2. add mstatus.vs initialization macro. The macro also enables floating unit. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-11-28fill exit syscall information to make semihosting workChih-Min Chao1-0/+4
Some simulators support semihosting feature to brigde syscall to host. The change keep the exit syscall and the arguments in the related registers. Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>
2019-08-15Don't truncate the LFSR to 32 bitsAndrew Waterman1-2/+2
This caused it to collapse to 0, preventing coherence_torture from doing anything interesting at all...
2019-02-19Support testing Sv48 with -DSv48 optionAndrew Waterman1-21/+47
2019-01-04Align entry points for RVC compilationAndrew Waterman1-0/+4
2018-09-23Avoid writing reserved values to pmpaddr CSRAndrew Waterman2-2/+4
2018-09-06Enable EXTRA_INIT macro to work in VM environment (#10)Michael McKeown2-0/+5
2017-11-27Rename sptbr to satpAndrew Waterman3-25/+25
2017-08-16Merge pull request #4 from riscv/sfence_memoryPalmer Dabbelt1-1/+1
Inform GCC that "sfence.vma" clobbers memory
2017-08-16Inform GCC that "sfence.vma" clobbers memoryPalmer Dabbelt1-1/+1
2017-07-03Fix physical load address for recent binutilspriv-1.10Andrew Waterman1-3/+6
2017-05-05bump encoding.hAndrew Waterman1-0/+3
2017-05-01Set ELF entry point correctlyAndrew Waterman3-11/+9
2017-03-30New PMP encodingAndrew Waterman3-7/+8
2017-03-29Test sstatus.SUM more thoroughly by keeping it usually disabledAndrew Waterman1-1/+6
2017-03-27Separate page faults from physical memory access exceptionsAndrew Waterman3-17/+22
2017-03-24Clean up physical memory test init codeAndrew Waterman1-5/+20
2017-03-24Avoid misa in physical memory testsAndrew Waterman1-2/+2
The spec allows it to be hardwired to 0, so don't rely on its value.
2017-03-23Align mtvec targetAndrew Waterman1-0/+1
2017-03-23Rely on assembler to provide PMP CSRsAndrew Waterman2-7/+6
2017-03-21Use gp for TESTNUM, so compiled C code won't touch itAndrew Waterman1-1/+1
2017-03-21Set up PMP if presentAndrew Waterman3-7/+71
2017-03-13Update encodingAndrew Waterman1-0/+3
2017-03-09WIP on priv-1.10Andrew Waterman3-61/+177
2017-03-02Check XLEN only after initializing mtvecAndrew Waterman1-1/+1
2016-12-06avoid non-standard predefined macrosAndrew Waterman5-10/+6
2016-08-26Disable interrupts during VM testsAndrew Waterman1-2/+3
The code doesn't support interrupts, and it was relying on the reset value of the mie register (which is undefined) to disable them.
2016-08-26Update encodingAndrew Waterman1-72/+341
2016-08-17Avoid division in VM testsAndrew Waterman2-6/+6
so we can use the same object code on processors without the M extension
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