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AgeCommit message (Expand)AuthorFilesLines
2014-11-22Revert "Enable support for the four custom instructions"Yunsup Lee1-72/+0
2014-11-06Improve VM env debug messagesAndrew Waterman1-6/+6
2014-10-24Merge pull request #1 from arunthomas/custom_instYunsup Lee1-0/+72
2014-10-23Enable support for the four custom instructionsArun Thomas1-0/+72
2014-04-03Sync encoding.h with opcodesStephen Twigg1-43/+61
2014-03-03need to modify status register *before* enabling interruptsYunsup Lee1-2/+2
2014-03-02Renumber uarch CSRs into custom CSR spaceYunsup Lee1-16/+16
2014-02-27enable interrupts *after* setting the evec registerYunsup Lee1-1/+1
2014-02-25make physical timer env work againYunsup Lee2-23/+47
2014-02-06fix recursive interrupts, and more improvements to codeYunsup Lee3-15/+29
2014-02-06Improve trap entry codeAndrew Waterman3-35/+23
2014-02-06Update CSRsAndrew Waterman1-48/+48
2014-02-06Update CSRsAndrew Waterman1-13/+96
2014-02-06fix vector exceptions on rocketYunsup Lee2-24/+15
2014-01-31Support RV32S testsAndrew Waterman1-0/+5
2014-01-31Use TESTNUM instead of x28 directlyAndrew Waterman2-29/+19
2014-01-20Update encoding.h to reflect JALR, RDCYCLE changesQuan Nguyen1-24/+24
2014-01-16Source test failure value from correct registerAndrew Waterman1-4/+4
2014-01-13Assume pc-relative addressingAndrew Waterman2-26/+26
2013-11-25Fix SLLI encodingAndrew Waterman1-2/+4
2013-11-24Update to new privileged modeAndrew Waterman7-178/+691
2013-11-13split out envs from riscv-testsYunsup Lee12-0/+1200
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