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authorAndrew Waterman <waterman@eecs.berkeley.edu>2013-11-24 14:25:22 -0800
committerAndrew Waterman <waterman@eecs.berkeley.edu>2013-11-24 14:25:22 -0800
commit9c4e0839779f302720173ad063fa25366cef21f7 (patch)
tree0fc4021f6287a68c1d1d033a4eaf0e6297029002 /v
parentf3545105d54ab746efac58b96e998a252cafd16b (diff)
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Update to new privileged mode
Diffstat (limited to 'v')
-rw-r--r--v/entry.S40
-rw-r--r--v/riscv_test.h6
-rw-r--r--v/vm.c18
3 files changed, 32 insertions, 32 deletions
diff --git a/v/entry.S b/v/entry.S
index 541abae..8dbf248 100644
--- a/v/entry.S
+++ b/v/entry.S
@@ -51,19 +51,19 @@ save_tf: # write the trap frame onto the stack
STORE x30,30*REGBYTES(x2)
STORE x31,31*REGBYTES(x2)
- mfpcr x3,sup0
+ csrr x3,sup0
STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0
- mfpcr x3,sup1
+ csrr x3,sup1
STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1
# get sr, epc, badvaddr, cause
- mfpcr x3,status # sr
+ csrr x3,status # sr
STORE x3,32*REGBYTES(x2)
- mfpcr x4,epc # epc
+ csrr x4,epc # epc
STORE x4,33*REGBYTES(x2)
- mfpcr x3,badvaddr # badvaddr
+ csrr x3,badvaddr # badvaddr
STORE x3,34*REGBYTES(x2)
- mfpcr x3,cause # cause
+ csrr x3,cause # cause
STORE x3,35*REGBYTES(x2)
# get faulting insn, if it wasn't a fetch-related trap
@@ -88,12 +88,12 @@ save_tf: # write the trap frame onto the stack
pop_tf: # write the trap frame onto the stack
# restore gprs
LOAD a1,32*REGBYTES(a0) # restore sr (should disable interrupts)
- mtpcr a1,status
+ csrw status,a1
LOAD x1,1*REGBYTES(a0)
- mtpcr x1,sup0
- LOAD x1,2*REGBYTES(a0)
- mtpcr x1,sup1
+ LOAD x2,2*REGBYTES(a0)
+ csrw sup0,x1
+ csrw sup1,x2
move x1,a0
LOAD x3,3*REGBYTES(x1)
LOAD x4,4*REGBYTES(x1)
@@ -127,18 +127,18 @@ pop_tf: # write the trap frame onto the stack
# gtfo!
LOAD x2,33*REGBYTES(x1)
- mtpcr x2,epc
- mfpcr x1,sup0
- mfpcr x2,sup1
- eret
+ csrw epc,x2
+ csrr x1,sup0
+ csrr x2,sup1
+ sret
.global trap_entry
trap_entry:
- mtpcr ra,sup0
- mtpcr x2,sup1
+ csrw sup0,ra
+ csrw sup1,x2
# coming from kernel?
- mfpcr ra,status
+ csrr ra,status
and ra,ra,SR_PS
bnez ra, 1f
@@ -146,9 +146,9 @@ trap_entry:
la x2,stack_top+MAX_TEST_PAGES*PGSIZE-SIZEOF_TRAPFRAME_T
jal save_tf
move sp,x2
- setpcr status, SR_EI
+ csrs status,SR_EI
move a0,x2
- mfpcr ra,status
+ csrr ra,status
and ra,ra,SR_EA
beqz ra, 2f
addi x2,x2,38*REGBYTES
@@ -160,7 +160,7 @@ trap_entry:
sub x2, sp, x2
jal save_tf
move sp,x2
- setpcr status, SR_EI
+ csrs status,SR_EI
move a0,x2
jal handle_trap
diff --git a/v/riscv_test.h b/v/riscv_test.h
index 20d0690..e129566 100644
--- a/v/riscv_test.h
+++ b/v/riscv_test.h
@@ -34,8 +34,8 @@ userstart: \
// Pass/Fail Macro
//-----------------------------------------------------------------------
-#define RVTEST_PASS li a0, 1; syscall;
-#define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; syscall;
+#define RVTEST_PASS li a0, 1; scall;
+#define RVTEST_FAIL sll a0, x28, 1; 1:beqz a0, 1b; or a0, a0, 1; scall;
//-----------------------------------------------------------------------
// Data Section Macro
@@ -51,7 +51,7 @@ userstart: \
// Supervisor mode definitions and macros
//-----------------------------------------------------------------------
-#include "../pcr.h"
+#include "../encoding.h"
#include "../hwacha_xcpt.h"
#define dword_bit_cmd(dw) ((dw >> 32) & 0x1)
diff --git a/v/vm.c b/v/vm.c
index 6b61c02..2c016ae 100644
--- a/v/vm.c
+++ b/v/vm.c
@@ -9,7 +9,7 @@ void pop_tf(trapframe_t*);
static void cputchar(int x)
{
- while (mtpcr(PCR_TOHOST, 0x0101000000000000 | (unsigned char)x));
+ while (swap_csr(tohost, 0x0101000000000000 | (unsigned char)x));
}
static void cputstring(const char* s)
@@ -21,7 +21,7 @@ static void cputstring(const char* s)
static void terminate(int code)
{
- while (mtpcr(PCR_TOHOST, code));
+ while (swap_csr(tohost, code));
while (1);
}
@@ -90,7 +90,7 @@ void handle_fault(unsigned long addr)
*RELOC(&freelist_tail) = 0;
*RELOC(&l3pt[addr/PGSIZE]) = node->addr | PTE_UW | PTE_UR | PTE_UX | PTE_SW | PTE_SR | PTE_SX | PTE_V;
- mtpcr(PCR_FATC, 0);
+ write_csr(fatc, 0);
assert(RELOC(&user_mapping[addr/PGSIZE])->addr == 0);
*RELOC(&user_mapping[addr/PGSIZE]) = *node;
@@ -166,7 +166,7 @@ static void emulate_vxcptrestore(trapframe_t* tf)
static void restore_vector(trapframe_t* tf)
{
- if (mfpcr(PCR_IMPL) == IMPL_ROCKET)
+ if (read_csr(impl) == IMPL_ROCKET)
do_vxcptrestore(tf->evac);
else
vxcptrestore(tf->evac);
@@ -229,7 +229,7 @@ out:
void vm_boot(long test_addr, long seed)
{
- while (mfpcr(PCR_HARTID) > 0); // only core 0 proceeds
+ while (read_csr(hartid) > 0); // only core 0 proceeds
assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t));
@@ -250,12 +250,12 @@ void vm_boot(long test_addr, long seed)
for (long i = 0; i < MAX_TEST_PAGES; i++)
l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | PTE_SW | PTE_SR | PTE_SX | PTE_V;
- mtpcr(PCR_PTBR, l1pt);
- mtpcr(PCR_SR, mfpcr(PCR_SR) | SR_VM | SR_EF);
+ write_csr(ptbr, l1pt);
+ write_csr(status, read_csr(status) | SR_VM | SR_EF);
// relocate
long adjustment = RELOC(0L), tmp;
- mtpcr(PCR_EVEC, (char*)&trap_entry + adjustment);
+ write_csr(evec, (char*)&trap_entry + adjustment);
asm volatile ("add sp, sp, %1\n"
"jal %0, 1f\n"
"1: add %0, %0, %1\n"
@@ -264,7 +264,7 @@ void vm_boot(long test_addr, long seed)
: "r"(adjustment));
memset(RELOC(&l3pt[0]), 0, MAX_TEST_PAGES*sizeof(pte_t));
- mtpcr(PCR_FATC, 0);
+ write_csr(fatc, 0);
trapframe_t tf;
memset(&tf, 0, sizeof(tf));