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| author | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-13 18:03:30 -0800 |
|---|---|---|
| committer | Yunsup Lee <yunsup@cs.berkeley.edu> | 2013-11-13 18:03:30 -0800 |
| commit | f3545105d54ab746efac58b96e998a252cafd16b (patch) | |
| tree | da4932d63a025a7f12cac970c588e9eb5465847e /p/riscv_test.h | |
| download | env-f3545105d54ab746efac58b96e998a252cafd16b.zip env-f3545105d54ab746efac58b96e998a252cafd16b.tar.gz env-f3545105d54ab746efac58b96e998a252cafd16b.tar.bz2 | |
split out envs from riscv-tests
Diffstat (limited to 'p/riscv_test.h')
| -rw-r--r-- | p/riscv_test.h | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h new file mode 100644 index 0000000..4253ef5 --- /dev/null +++ b/p/riscv_test.h @@ -0,0 +1,117 @@ +#ifndef _ENV_PHYSICAL_SINGLE_CORE_H +#define _ENV_PHYSICAL_SINGLE_CORE_H + +#include "../pcr.h" +#include "../hwacha_xcpt.h" + +//----------------------------------------------------------------------- +// Begin Macro +//----------------------------------------------------------------------- + +#define RVTEST_RV64U \ + .macro init; \ + .endm + +#define RVTEST_RV64UF \ + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV64UV \ + .macro init; \ + RVTEST_FP_ENABLE; \ + RVTEST_VEC_ENABLE; \ + .endm + +#define RVTEST_RV32U \ + .macro init; \ + RVTEST_32_ENABLE; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + RVTEST_32_ENABLE; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV32UV \ + .macro init; \ + RVTEST_32_ENABLE; \ + RVTEST_FP_ENABLE; \ + RVTEST_VEC_ENABLE; \ + .endm + +#define RVTEST_RV64S \ + .macro init; \ + .endm + +#define RVTEST_32_ENABLE \ + clearpcr status, SR_S64 \ + +#define RVTEST_FP_ENABLE \ + setpcr status, SR_EF; \ + mfpcr a0, status; \ + and a0, a0, SR_EF; \ + bnez a0, 2f; \ + RVTEST_PASS; \ +2:fssr x0; \ + +#define RVTEST_VEC_ENABLE \ + setpcr status, SR_EA; \ + mfpcr a0, status; \ + and a0, a0, SR_EA; \ + bnez a0, 2f; \ + RVTEST_PASS; \ +2: \ + +#define RISCV_MULTICORE_DISABLE \ + mfpcr a0, hartid; 1: bnez a0, 1b; \ + +#define EXTRA_INIT + +#define RVTEST_CODE_BEGIN \ + .text; \ + .align 4; \ + .global _start; \ +_start: \ + RISCV_MULTICORE_DISABLE; \ + init; \ + EXTRA_INIT; \ + +//----------------------------------------------------------------------- +// End Macro +//----------------------------------------------------------------------- + +#define RVTEST_CODE_END \ + +//----------------------------------------------------------------------- +// Pass/Fail Macro +//----------------------------------------------------------------------- + +#define RVTEST_PASS \ + fence; \ + li x1, 1; \ + mtpcr x1, tohost; \ +1: b 1b; \ + +#define RVTEST_FAIL \ + fence; \ + beqz x28, 1f; \ + sll x28, x28, 1; \ + or x28, x28, 1; \ + mtpcr x28, tohost; \ +1: b 1b; \ + +//----------------------------------------------------------------------- +// Data Section Macro +//----------------------------------------------------------------------- + +//#define RVTEST_DATA_BEGIN EXTRA_DATA +//#define RVTEST_DATA_END + +#define EXTRA_DATA + +#define RVTEST_DATA_BEGIN EXTRA_DATA .align 4; .global begin_signature; begin_signature: +#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: + +#endif |