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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:38:41 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-03-12 17:39:24 -0700 |
| commit | 3a2ed4c0966add8f9730c3962a784cc423891663 (patch) | |
| tree | 1baf3a59376649cdf7abe80693261b0bd4beb0c8 /p/riscv_test.h | |
| parent | e742249aff0ea2d1cabe86bdebca836d0e3ab4d4 (diff) | |
| download | env-3a2ed4c0966add8f9730c3962a784cc423891663.zip env-3a2ed4c0966add8f9730c3962a784cc423891663.tar.gz env-3a2ed4c0966add8f9730c3962a784cc423891663.tar.bz2 | |
Update to new privileged spec
Diffstat (limited to 'p/riscv_test.h')
| -rw-r--r-- | p/riscv_test.h | 90 |
1 files changed, 76 insertions, 14 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index ad9bfdc..36d723d 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -43,30 +43,55 @@ RVTEST_VEC_ENABLE; \ .endm +#define RVTEST_RV64M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + .endm + #define RVTEST_RV64S \ .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ + .endm + +#define RVTEST_RV32M \ + .macro init; \ + RVTEST_ENABLE_MACHINE; \ + RVTEST_32_ENABLE; \ .endm #define RVTEST_RV32S \ .macro init; \ + RVTEST_ENABLE_SUPERVISOR; \ RVTEST_32_ENABLE; \ .endm #define RVTEST_32_ENABLE \ - li a0, SR_S64; \ - csrc status, a0; \ + li a0, MSTATUS64_UA >> 31; \ + slli a0, a0, 31; \ + csrc mstatus, a0; \ + li a0, MSTATUS64_SA >> 31; \ + slli a0, a0, 31; \ + csrc mstatus, a0; \ + +#define RVTEST_ENABLE_SUPERVISOR \ + li a0, MSTATUS_PRV1 & (MSTATUS_PRV1 >> 1); \ + csrs mstatus, a0; \ + +#define RVTEST_ENABLE_MACHINE \ + li a0, MSTATUS_PRV1; \ + csrs mstatus, a0; \ #define RVTEST_FP_ENABLE \ - li a0, SR_EF; \ - csrs status, a0; \ - csrr a1, status; \ + li a0, SSTATUS_FS & (SSTATUS_FS >> 1); \ + csrs sstatus, a0; \ + csrr a1, sstatus; \ and a0, a0, a1; \ bnez a0, 2f; \ RVTEST_PASS; \ 2:fssr x0; \ #define RVTEST_VEC_ENABLE \ - li a0, SR_EA; \ + li a0, SSSTATUS_XS & (SSTATUS_XS >> 1); \ csrs status, a0; \ csrr a1, status; \ and a0, a0, a1; \ @@ -76,26 +101,64 @@ #define RISCV_MULTICORE_DISABLE \ csrr a0, hartid; \ - 1: bnez a0, 1b; \ + 1: bnez a0, 1b #define EXTRA_INIT #define EXTRA_INIT_TIMER #define RVTEST_CODE_BEGIN \ .text; \ - .align 4; \ - .global _start; \ + .align 6; \ +tvec_user: \ + la t5, mcall; \ + csrr t6, mepc; \ + beq t5, t6, write_tohost; \ + li t5, 0xbadbad0; \ + csrr t6, stvec; \ + bne t5, t6, 2f; \ + ori TESTNUM, TESTNUM, 1337; /* some other exception occurred */ \ + write_tohost: csrw tohost, TESTNUM; \ + j write_tohost; \ + 2: mrts; \ + .align 6; \ +tvec_supervisor: \ + csrr t5, mcause; \ + bgez t5, tvec_user; \ + mrts; \ + .align 6; \ +tvec_hypervisor: \ + RVTEST_FAIL; /* no hypervisor */ \ + .align 6; \ +tvec_machine: \ + .weak mtvec; \ + la t5, mcall; \ + csrr t6, mepc; \ + beq t5, t6, write_tohost; \ + la t5, mtvec; \ +1: beqz t5, 1b; \ + j mtvec; \ + .align 6; \ + .globl _start; \ _start: \ RISCV_MULTICORE_DISABLE; \ + li t0, 0xbadbad0; csrw stvec, t0; \ + li t0, MSTATUS_PRV1; csrc mstatus, t0; \ init; \ EXTRA_INIT; \ EXTRA_INIT_TIMER; \ + la t0, 1f; \ + csrw mepc, t0; \ + csrr a0, hartid; \ + mret; \ +1: //----------------------------------------------------------------------- // End Macro //----------------------------------------------------------------------- #define RVTEST_CODE_END \ +mcall: mcall; \ + j mcall //----------------------------------------------------------------------- // Pass/Fail Macro @@ -103,17 +166,16 @@ _start: \ #define RVTEST_PASS \ fence; \ - csrw tohost, 1; \ -1: j 1b; \ + li TESTNUM, 1; \ + j mcall #define TESTNUM x28 #define RVTEST_FAIL \ fence; \ - beqz TESTNUM, 1f; \ +1: beqz TESTNUM, 1b; \ sll TESTNUM, TESTNUM, 1; \ or TESTNUM, TESTNUM, 1; \ - csrw tohost, TESTNUM; \ -1: j 1b; \ + j mcall //----------------------------------------------------------------------- // Data Section Macro |