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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:31:23 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2015-09-20 23:31:23 -0700 |
| commit | 0bf56e2156ad5393ec2997e4f3dfba98778e8f1f (patch) | |
| tree | 2ef7c198f94720b118c02c3aaab8a3b69dbbbb89 /p/riscv_test.h | |
| parent | cdf86f59e5706d1c35371b555892fe7b8ab2b01d (diff) | |
| download | env-0bf56e2156ad5393ec2997e4f3dfba98778e8f1f.zip env-0bf56e2156ad5393ec2997e4f3dfba98778e8f1f.tar.gz env-0bf56e2156ad5393ec2997e4f3dfba98778e8f1f.tar.bz2 | |
Remove Hwacha v3 support
Diffstat (limited to 'p/riscv_test.h')
| -rw-r--r-- | p/riscv_test.h | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 23d33b7..6e35b18 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -4,7 +4,6 @@ #define _ENV_PHYSICAL_SINGLE_CORE_H #include "../encoding.h" -#include "../hwacha_xcpt.h" //----------------------------------------------------------------------- // Begin Macro @@ -19,12 +18,6 @@ RVTEST_FP_ENABLE; \ .endm -#define RVTEST_RV64UV \ - .macro init; \ - RVTEST_FP_ENABLE; \ - RVTEST_VEC_ENABLE; \ - .endm - #define RVTEST_RV32U \ .macro init; \ .endm @@ -34,12 +27,6 @@ RVTEST_FP_ENABLE; \ .endm -#define RVTEST_RV32UV \ - .macro init; \ - RVTEST_FP_ENABLE; \ - RVTEST_VEC_ENABLE; \ - .endm - #define RVTEST_RV64M \ .macro init; \ RVTEST_ENABLE_MACHINE; \ @@ -53,7 +40,6 @@ #define RVTEST_RV64SV \ .macro init; \ RVTEST_ENABLE_SUPERVISOR; \ - RVTEST_VEC_ENABLE; \ .endm #define RVTEST_RV32M \ @@ -85,10 +71,6 @@ csrs mstatus, a0; \ csrwi fcsr, 0 -#define RVTEST_VEC_ENABLE \ - li a0, SSTATUS_XS & (SSTATUS_XS >> 1); \ - csrs sstatus, a0; \ - #define RISCV_MULTICORE_DISABLE \ csrr a0, mhartid; \ 1: bnez a0, 1b @@ -125,15 +107,6 @@ tvec_supervisor: \ csrr t5, mcause; \ bgez t5, tvec_user; \ mrts_routine: \ - li t5, MSTATUS_XS; \ - csrr t6, mstatus; \ - and t5, t5, t6; \ - beqz t5, skip_vector_cause_aux; \ - vxcptcause t5; \ - csrw mcause, t5; \ - vxcptaux t5; \ - csrw mbadaddr, t5; \ - skip_vector_cause_aux: \ mrts; \ .align 6; \ tvec_hypervisor: \ |