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| author | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:00:32 -0700 |
|---|---|---|
| committer | Andrew Waterman <waterman@cs.berkeley.edu> | 2016-06-08 20:00:32 -0700 |
| commit | 2feb57e3bfb9814b2b21b0dfdfbe2c7ef26db5f4 (patch) | |
| tree | 11f4f77ff9095b3c7f936c7988cdc97c172ad43c /encoding.h | |
| parent | e0d1ea452c2a40ca47ec720e7da8c31daa317307 (diff) | |
| download | env-2feb57e3bfb9814b2b21b0dfdfbe2c7ef26db5f4.zip env-2feb57e3bfb9814b2b21b0dfdfbe2c7ef26db5f4.tar.gz env-2feb57e3bfb9814b2b21b0dfdfbe2c7ef26db5f4.tar.bz2 | |
Update encoding.h
Diffstat (limited to 'encoding.h')
| -rw-r--r-- | encoding.h | 50 |
1 files changed, 50 insertions, 0 deletions
@@ -33,6 +33,29 @@ #define SSTATUS32_SD 0x80000000 #define SSTATUS64_SD 0x8000000000000000 +#define DCSR_XDEBUGVER (3U<<30) +#define DCSR_NDRESET (1<<29) +#define DCSR_FULLRESET (1<<28) +#define DCSR_HWBPCOUNT (0xfff<<16) +#define DCSR_EBREAKM (1<<15) +#define DCSR_EBREAKH (1<<14) +#define DCSR_EBREAKS (1<<13) +#define DCSR_EBREAKU (1<<12) +#define DCSR_STOPCYCLE (1<<10) +#define DCSR_STOPTIME (1<<9) +#define DCSR_CAUSE (7<<6) +#define DCSR_DEBUGINT (1<<5) +#define DCSR_HALT (1<<3) +#define DCSR_STEP (1<<2) +#define DCSR_PRV (3<<0) + +#define DCSR_CAUSE_NONE 0 +#define DCSR_CAUSE_SWBP 1 +#define DCSR_CAUSE_HWBP 2 +#define DCSR_CAUSE_DEBUGINT 3 +#define DCSR_CAUSE_STEP 4 +#define DCSR_CAUSE_HALT 5 + #define MIP_SSIP (1 << IRQ_S_SOFT) #define MIP_HSIP (1 << IRQ_H_SOFT) #define MIP_MSIP (1 << IRQ_M_SOFT) @@ -77,6 +100,16 @@ #define EXT_IO_BASE 0x40000000 #define DRAM_BASE 0x80000000 +// breakpoint control fields +#define BPCONTROL_X 0x00000001 +#define BPCONTROL_W 0x00000002 +#define BPCONTROL_R 0x00000004 +#define BPCONTROL_U 0x00000008 +#define BPCONTROL_S 0x00000010 +#define BPCONTROL_H 0x00000020 +#define BPCONTROL_M 0x00000040 +#define BPCONTROL_MATCHCOND 0x00000180 + // page table entry (PTE) fields #define PTE_V 0x001 // Valid #define PTE_TYPE 0x01E // Type @@ -363,6 +396,8 @@ #define MASK_HRET 0xffffffff #define MATCH_MRET 0x30200073 #define MASK_MRET 0xffffffff +#define MATCH_DRET 0x7b200073 +#define MASK_DRET 0xffffffff #define MATCH_SFENCE_VM 0x10400073 #define MASK_SFENCE_VM 0xfff07fff #define MATCH_WFI 0x10500073 @@ -672,6 +707,13 @@ #define CSR_MSCYCLE_DELTA 0x704 #define CSR_MSTIME_DELTA 0x705 #define CSR_MSINSTRET_DELTA 0x706 +#define CSR_TDRSELECT 0x7a0 +#define CSR_TDRDATA1 0x7a1 +#define CSR_TDRDATA2 0x7a2 +#define CSR_TDRDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 #define CSR_MCYCLE 0xf00 #define CSR_MTIME 0xf01 #define CSR_MINSTRET 0xf02 @@ -799,6 +841,7 @@ DECLARE_INSN(uret, MATCH_URET, MASK_URET) DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) +DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) @@ -974,6 +1017,13 @@ DECLARE_CSR(muinstret_delta, CSR_MUINSTRET_DELTA) DECLARE_CSR(mscycle_delta, CSR_MSCYCLE_DELTA) DECLARE_CSR(mstime_delta, CSR_MSTIME_DELTA) DECLARE_CSR(msinstret_delta, CSR_MSINSTRET_DELTA) +DECLARE_CSR(tdrselect, CSR_TDRSELECT) +DECLARE_CSR(tdrdata1, CSR_TDRDATA1) +DECLARE_CSR(tdrdata2, CSR_TDRDATA2) +DECLARE_CSR(tdrdata3, CSR_TDRDATA3) +DECLARE_CSR(dcsr, CSR_DCSR) +DECLARE_CSR(dpc, CSR_DPC) +DECLARE_CSR(dscratch, CSR_DSCRATCH) DECLARE_CSR(mcycle, CSR_MCYCLE) DECLARE_CSR(mtime, CSR_MTIME) DECLARE_CSR(minstret, CSR_MINSTRET) |