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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-02 15:47:25 -0800 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-02 15:47:25 -0800 |
| commit | b3e14827904c2b1247171f4f1522be397349e7ea (patch) | |
| tree | 95a97a168205086d0eb58673ea4d728d1c1cc7e6 | |
| parent | 9e219c9ca70459bfda9067d637bb8bf52c5f0326 (diff) | |
| download | env-b3e14827904c2b1247171f4f1522be397349e7ea.zip env-b3e14827904c2b1247171f4f1522be397349e7ea.tar.gz env-b3e14827904c2b1247171f4f1522be397349e7ea.tar.bz2 | |
Check XLEN only after initializing mtvec
| -rw-r--r-- | p/riscv_test.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 0a5bf51..1da083c 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -121,10 +121,10 @@ handle_exception: \ j write_tohost; \ reset_vector: \ RISCV_MULTICORE_DISABLE; \ - CHECK_XLEN; \ li TESTNUM, 0; \ la t0, trap_vector; \ csrw mtvec, t0; \ + CHECK_XLEN; \ csrwi medeleg, 0; \ csrwi mideleg, 0; \ csrwi mie, 0; \ |