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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-24 12:51:02 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-24 12:51:02 -0700 |
| commit | 3dc64058de56fbac3b793e20707739f0b985303c (patch) | |
| tree | 6c3cea9223215a28d2cde94bb3fdd1a818dd13a9 | |
| parent | 0f589618ad654d808932c81f6f15d64e2e9e4651 (diff) | |
| download | env-3dc64058de56fbac3b793e20707739f0b985303c.zip env-3dc64058de56fbac3b793e20707739f0b985303c.tar.gz env-3dc64058de56fbac3b793e20707739f0b985303c.tar.bz2 | |
Clean up physical memory test init code
| -rw-r--r-- | p/riscv_test.h | 25 |
1 files changed, 20 insertions, 5 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index 3b3fcaa..9ed6ebc 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -53,14 +53,30 @@ # define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: #endif -#define INIT_SPTBR \ +#define INIT_PMP \ la t0, 1f; \ csrw mtvec, t0; \ - csrwi sptbr, 0; \ li t0, -1; /* Set up a PMP to permit all accesses */ \ csrw pmpaddr0, t0; \ li t0, PMP_EN | PMP_NAPOT | PMP_M | PMP_R | PMP_W | PMP_X; \ csrw pmpcfg0, t0; \ + .align 2; \ +1: + +#define INIT_SPTBR \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi sptbr, 0; \ + .align 2; \ +1: + +#define DELEGATE_NO_TRAPS \ + la t0, 1f; \ + csrw mtvec, t0; \ + csrwi medeleg, 0; \ + csrwi mideleg, 0; \ + csrwi mie, 0; \ + .align 2; \ 1: #define RVTEST_ENABLE_SUPERVISOR \ @@ -127,13 +143,12 @@ handle_exception: \ reset_vector: \ RISCV_MULTICORE_DISABLE; \ INIT_SPTBR; \ + INIT_PMP; \ + DELEGATE_NO_TRAPS; \ li TESTNUM, 0; \ la t0, trap_vector; \ csrw mtvec, t0; \ CHECK_XLEN; \ - csrwi medeleg, 0; \ - csrwi mideleg, 0; \ - csrwi mie, 0; \ /* if an stvec_handler is defined, delegate exceptions to it */ \ la t0, stvec_handler; \ beqz t0, 1f; \ |