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| author | Andrew Waterman <andrew@sifive.com> | 2017-03-24 12:50:26 -0700 |
|---|---|---|
| committer | Andrew Waterman <andrew@sifive.com> | 2017-03-24 12:50:26 -0700 |
| commit | 0f589618ad654d808932c81f6f15d64e2e9e4651 (patch) | |
| tree | bc41f5fb51d6a3cb45d18ef27a4c3566a9aae707 | |
| parent | 14cdc2888b1ad430c6f5c21b27ab8bd4ed13faab (diff) | |
| download | env-0f589618ad654d808932c81f6f15d64e2e9e4651.zip env-0f589618ad654d808932c81f6f15d64e2e9e4651.tar.gz env-0f589618ad654d808932c81f6f15d64e2e9e4651.tar.bz2 | |
Avoid misa in physical memory tests
The spec allows it to be hardwired to 0, so don't rely on its value.
| -rw-r--r-- | p/riscv_test.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/p/riscv_test.h b/p/riscv_test.h index e28c5e5..3b3fcaa 100644 --- a/p/riscv_test.h +++ b/p/riscv_test.h @@ -48,9 +48,9 @@ .endm #if __riscv_xlen == 64 -# define CHECK_XLEN csrr a0, misa; bltz a0, 1f; RVTEST_PASS; 1: +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bgez a0, 1f; RVTEST_PASS; 1: #else -# define CHECK_XLEN csrr a0, misa; bgez a0, 1f; RVTEST_PASS; 1: +# define CHECK_XLEN li a0, 1; slli a0, a0, 31; bltz a0, 1f; RVTEST_PASS; 1: #endif #define INIT_SPTBR \ |