#!/usr/bin/env python import argparse import binascii import random import sys import tempfile import time import os import targets import testlib from testlib import assertEqual, assertNotEqual, assertIn, assertNotIn from testlib import assertGreater, assertRegexpMatches, assertLess from testlib import GdbTest, GdbSingleHartTest, TestFailed from testlib import assertTrue MSTATUS_UIE = 0x00000001 MSTATUS_SIE = 0x00000002 MSTATUS_HIE = 0x00000004 MSTATUS_MIE = 0x00000008 MSTATUS_UPIE = 0x00000010 MSTATUS_SPIE = 0x00000020 MSTATUS_HPIE = 0x00000040 MSTATUS_MPIE = 0x00000080 MSTATUS_SPP = 0x00000100 MSTATUS_HPP = 0x00000600 MSTATUS_MPP = 0x00001800 MSTATUS_FS = 0x00006000 MSTATUS_XS = 0x00018000 MSTATUS_MPRV = 0x00020000 MSTATUS_PUM = 0x00040000 MSTATUS_MXR = 0x00080000 MSTATUS_VM = 0x1F000000 MSTATUS32_SD = 0x80000000 MSTATUS64_SD = 0x8000000000000000 # pylint: disable=abstract-method def ihex_line(address, record_type, data): assert len(data) < 128 line = ":%02X%04X%02X" % (len(data), address, record_type) check = len(data) check += address % 256 check += address >> 8 check += record_type for char in data: value = ord(char) check += value line += "%02X" % value line += "%02X\n" % ((256-check)%256) return line def srec_parse(line): assert line.startswith('S') typ = line[:2] count = int(line[2:4], 16) data = "" if typ == 'S0': # header return 0, 0, 0 elif typ == 'S3': # data with 32-bit address # Any higher bits were chopped off. address = int(line[4:12], 16) for i in range(6, count+1): data += "%c" % int(line[2*i:2*i+2], 16) # Ignore the checksum. return 3, address, data elif typ == 'S7': # ignore execution start field return 7, 0, 0 else: raise TestFailed("Unsupported SREC type %r." % typ) def readable_binary_string(s): return "".join("%02x" % ord(c) for c in s) class SimpleRegisterTest(GdbTest): def check_reg(self, name, alias): a = random.randrange(1< last_pc and pc - last_pc <= 4: advances += 1 else: jumps += 1 last_pc = pc # Some basic sanity that we're not running between breakpoints or # something. assertGreater(jumps, 1) assertGreater(advances, 5) class DebugExit(DebugTest): def test(self): self.exit() class DebugSymbols(DebugTest): def test(self): bp = self.gdb.b("main") output = self.gdb.c() assertIn(", main ", output) self.gdb.command("delete %d" % bp) bp = self.gdb.b("rot13") output = self.gdb.c() assertIn(", rot13 ", output) self.gdb.command("delete %d" % bp) class DebugBreakpoint(DebugTest): def test(self): self.gdb.b("rot13") # The breakpoint should be hit exactly 2 times. for _ in range(2): output = self.gdb.c() self.gdb.p("$pc") assertIn("Breakpoint ", output) assertIn("rot13 ", output) self.exit() class Hwbp1(DebugTest): def test(self): if self.hart.instruction_hardware_breakpoint_count < 1: return 'not_applicable' if not self.hart.honors_tdata1_hmode: # Run to main before setting the breakpoint, because startup code # will otherwise clear the trigger that we set. self.gdb.b("main") self.gdb.c() self.gdb.command("delete") self.gdb.hbreak("rot13") # The breakpoint should be hit exactly 2 times. for _ in range(2): output = self.gdb.c() self.gdb.p("$pc") assertRegexpMatches(output, r"[bB]reakpoint") assertIn("rot13 ", output) self.gdb.b("_exit") self.exit() class Hwbp2(DebugTest): def test(self): if self.hart.instruction_hardware_breakpoint_count < 2: return 'not_applicable' self.gdb.command("delete") self.gdb.hbreak("main") self.gdb.hbreak("rot13") # We should hit 3 breakpoints. for expected in ("main", "rot13", "rot13"): output = self.gdb.c() self.gdb.p("$pc") assertRegexpMatches(output, r"[bB]reakpoint") assertIn("%s " % expected, output) self.gdb.command("delete") self.gdb.b("_exit") self.exit() class TooManyHwbp(DebugTest): def test(self): for i in range(30): self.gdb.hbreak("*rot13 + %d" % (i * 4)) output = self.gdb.c(checkOutput=False) assertIn("Cannot insert hardware breakpoint", output) # Clean up, otherwise the hardware breakpoints stay set and future # tests may fail. self.gdb.command("D") class Registers(DebugTest): def test(self): # Get to a point in the code where some registers have actually been # used. self.gdb.b("rot13") self.gdb.c() self.gdb.c() # Try both forms to test gdb. for cmd in ("info all-registers", "info registers all"): output = self.gdb.command(cmd, ops=100) for reg in ('zero', 'ra', 'sp', 'gp', 'tp'): assertIn(reg, output) for line in output.splitlines(): assertRegexpMatches(line, r"^\S") #TODO # mcpuid is one of the few registers that should have the high bit set # (for rv64). # Leave this commented out until gdb and spike agree on the encoding of # mcpuid (which is going to be renamed to misa in any case). #assertRegexpMatches(output, ".*mcpuid *0x80") #TODO: # The instret register should always be changing. #last_instret = None #for _ in range(5): # instret = self.gdb.p("$instret") # assertNotEqual(instret, last_instret) # last_instret = instret # self.gdb.stepi() self.exit() class UserInterrupt(DebugTest): def test(self): """Sending gdb ^C while the program is running should cause it to halt.""" self.gdb.b("main:start") self.gdb.c() self.gdb.p("i=123") self.gdb.c(wait=False) time.sleep(2) output = self.gdb.interrupt() assert "main" in output assertGreater(self.gdb.p("j"), 10) self.gdb.p("i=0") self.exit() class InterruptTest(GdbSingleHartTest): compile_args = ("programs/interrupt.c",) def early_applicable(self): return self.target.supports_clint_mtime def setup(self): self.gdb.load() def test(self): self.gdb.b("main") output = self.gdb.c() assertIn(" main ", output) self.gdb.b("trap_entry") output = self.gdb.c() assertIn(" trap_entry ", output) assertEqual(self.gdb.p("$mip") & 0x80, 0x80) assertEqual(self.gdb.p("interrupt_count"), 0) # You'd expect local to still be 0, but it looks like spike doesn't # jump to the interrupt handler immediately after the write to # mtimecmp. assertLess(self.gdb.p("local"), 1000) self.gdb.command("delete breakpoints") for _ in range(10): self.gdb.c(wait=False) time.sleep(2) self.gdb.interrupt() interrupt_count = self.gdb.p("interrupt_count") local = self.gdb.p("local") if interrupt_count > 1000 and \ local > 1000: return assertGreater(interrupt_count, 1000) assertGreater(local, 1000) def postMortem(self): GdbSingleHartTest.postMortem(self) self.gdb.p("*((long long*) 0x200bff8)") self.gdb.p("*((long long*) 0x2004000)") self.gdb.p("interrupt_count") self.gdb.p("local") class MulticoreRegTest(GdbTest): compile_args = ("programs/infinite_loop.S", "-DMULTICORE") def early_applicable(self): return len(self.target.harts) > 1 def setup(self): self.gdb.load() for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.p("$pc=_start") def test(self): # Run to main for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.b("main") self.gdb.c() assertIn("main", self.gdb.where()) self.gdb.command("delete breakpoints") # Run through the entire loop. for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.b("main_end") self.gdb.c() assertIn("main_end", self.gdb.where()) hart_ids = [] for hart in self.target.harts: self.gdb.select_hart(hart) # Check register values. hart_id = self.gdb.p("$x1") assertNotIn(hart_id, hart_ids) hart_ids.append(hart_id) for n in range(2, 32): value = self.gdb.p("$x%d" % n) assertEqual(value, hart_ids[-1] + n - 1) # Confirmed that we read different register values for different harts. # Write a new value to x1, and run through the add sequence again. for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.p("$x1=0x%x" % (hart.index * 0x800)) self.gdb.p("$pc=main_post_csrr") self.gdb.c() for hart in self.target.harts: self.gdb.select_hart(hart) assertIn("main", self.gdb.where()) # Check register values. for n in range(1, 32): value = self.gdb.p("$x%d" % n) assertEqual(value, hart.index * 0x800 + n - 1) #class MulticoreRunHaltStepiTest(GdbTest): # compile_args = ("programs/multicore.c", "-DMULTICORE") # # def early_applicable(self): # return len(self.target.harts) > 1 # # def setup(self): # self.gdb.load() # for hart in self.target.harts: # self.gdb.select_hart(hart) # self.gdb.p("$mhartid") # self.gdb.p("$pc=_start") # # def test(self): # previous_hart_count = [0 for h in self.target.harts] # previous_interrupt_count = [0 for h in self.target.harts] # # Check 10 times # for i in range(10): # # 3 attempts for each time we want the check to pass # for attempt in range(3): # self.gdb.global_command("echo round %d attempt %d\\n" % (i, # attempt)) # self.gdb.c_all(wait=False) # time.sleep(2) # self.gdb.interrupt_all() # hart_count = self.gdb.p("hart_count") # interrupt_count = self.gdb.p("interrupt_count") # ok = True # for i, h in enumerate(self.target.harts): # if hart_count[i] <= previous_hart_count[i]: # ok = False # break # if interrupt_count[i] <= previous_interrupt_count[i]: # ok = False # break # self.gdb.p("$mie") # self.gdb.p("$mip") # self.gdb.p("$mstatus") # self.gdb.p("$priv") # self.gdb.p("buf", fmt="") # self.gdb.select_hart(h) # pc = self.gdb.p("$pc") # self.gdb.stepi() # stepped_pc = self.gdb.p("$pc") # assertNotEqual(pc, stepped_pc) # previous_hart_count = hart_count # previous_interrupt_count = interrupt_count # if ok: # break # else: # assert False, \ # "hart count or interrupt didn't increment as expected" class MulticoreRunAllHaltOne(GdbTest): compile_args = ("programs/multicore.c", "-DMULTICORE") def early_applicable(self): return len(self.target.harts) > 1 def setup(self): self.gdb.select_hart(self.target.harts[0]) self.gdb.load() for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.p("$pc=_start") def test(self): if not self.gdb.one_hart_per_gdb(): return 'not_applicable' # Run harts in reverse order for h in reversed(self.target.harts): self.gdb.select_hart(h) self.gdb.c(wait=False) self.gdb.interrupt() # Give OpenOCD time to call poll() on both harts, which is what causes # the bug. time.sleep(1) self.gdb.p("buf", fmt="") class MulticoreRtosSwitchActiveHartTest(GdbTest): compile_args = ("programs/multicore.c", "-DMULTICORE") def early_applicable(self): return len(self.target.harts) > 1 def setup(self): self.gdb.select_hart(self.target.harts[0]) self.gdb.load() for hart in self.target.harts: self.gdb.select_hart(hart) self.gdb.p("$pc=_start") def test(self): if self.gdb.one_hart_per_gdb(): return 'not_applicable' # Set breakpoint near '_start' label to increase the chances of a # situation when all harts hit breakpoint immediately and # simultaneously. self.gdb.b("set_trap_handler") # Check that all harts hit breakpoint one by one. for _ in range(len(self.target.harts)): output = self.gdb.c() assertIn("hit Breakpoint", output) assertIn("set_trap_handler", output) assertNotIn("received signal SIGTRAP", output) class StepTest(GdbSingleHartTest): compile_args = ("programs/step.S", ) def setup(self): self.gdb.load() self.gdb.b("main") self.gdb.c() def test(self): main_address = self.gdb.p("$pc") if self.hart.extensionSupported("c"): sequence = (4, 8, 0xc, 0xe, 0x14, 0x18, 0x22, 0x1c, 0x24, 0x24) else: sequence = (4, 8, 0xc, 0x10, 0x18, 0x1c, 0x28, 0x20, 0x2c, 0x2c) for expected in sequence: self.gdb.stepi() pc = self.gdb.p("$pc") assertEqual("%x" % (pc - main_address), "%x" % expected) class JumpHbreak(GdbSingleHartTest): """'jump' resumes execution at location. Execution stops again immediately if there is a breakpoint there. That second line can be trouble.""" compile_args = ("programs/trigger.S", ) def early_applicable(self): return self.hart.instruction_hardware_breakpoint_count >= 1 def setup(self): self.gdb.load() self.gdb.hbreak("main") self.gdb.c() self.gdb.command("delete 1") def test(self): self.gdb.b("read_loop") self.gdb.command("hbreak just_before_read_loop") output = self.gdb.command("jump just_before_read_loop") assertRegexpMatches(output, r"Breakpoint \d, just_before_read_loop ") output = self.gdb.c() assertRegexpMatches(output, r"Breakpoint \d, read_loop ") class TriggerTest(GdbSingleHartTest): compile_args = ("programs/trigger.S", ) def setup(self): self.gdb.load() self.gdb.b("main") self.gdb.c() self.gdb.command("delete") def exit(self): self.gdb.command("delete") self.gdb.b("_exit") output = self.gdb.c() assertIn("Breakpoint", output) assertIn("_exit", output) class TriggerExecuteInstant(TriggerTest): """Test an execute breakpoint on the first instruction executed out of debug mode.""" def test(self): main_address = self.gdb.p("$pc") self.gdb.command("hbreak *0x%x" % (main_address + 4)) self.gdb.c() assertEqual(self.gdb.p("$pc"), main_address+4) # FIXME: Triggers aren't quite working yet #class TriggerLoadAddress(TriggerTest): # def test(self): # self.gdb.command("rwatch *((&data)+1)") # output = self.gdb.c() # assertIn("read_loop", output) # assertEqual(self.gdb.p("$a0"), # self.gdb.p("(&data)+1")) # self.exit() class TriggerLoadAddressInstant(TriggerTest): """Test a load address breakpoint on the first instruction executed out of debug mode.""" def test(self): self.gdb.command("b just_before_read_loop") self.gdb.c() read_loop = self.gdb.p("&read_loop") read_again = self.gdb.p("&read_again") data = self.gdb.p("&data") self.gdb.command("rwatch *0x%x" % data) self.gdb.c() # Accept hitting the breakpoint before or after the load instruction. assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) self.gdb.c() assertIn(self.gdb.p("$pc"), [read_again, read_again + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) # FIXME: Triggers aren't quite working yet #class TriggerStoreAddress(TriggerTest): # def test(self): # self.gdb.command("watch *((&data)+3)") # output = self.gdb.c() # assertIn("write_loop", output) # assertEqual(self.gdb.p("$a0"), # self.gdb.p("(&data)+3")) # self.exit() class TriggerStoreAddressInstant(TriggerTest): def test(self): """Test a store address breakpoint on the first instruction executed out of debug mode.""" self.gdb.command("b just_before_write_loop") self.gdb.c() write_loop = self.gdb.p("&write_loop") data = self.gdb.p("&data") self.gdb.command("watch *0x%x" % data) self.gdb.c() # Accept hitting the breakpoint before or after the store instruction. assertIn(self.gdb.p("$pc"), [write_loop, write_loop + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) class TriggerDmode(TriggerTest): def early_applicable(self): return self.hart.honors_tdata1_hmode def check_triggers(self, tdata1_lsbs, tdata2): dmode = 1 << (self.hart.xlen-5) triggers = [] if self.hart.xlen == 32: xlen_type = 'int' elif self.hart.xlen == 64: xlen_type = 'long long' else: raise NotImplementedError dmode_count = 0 i = 0 for i in range(16): tdata1 = self.gdb.p("((%s *)&data)[%d]" % (xlen_type, 2*i)) if tdata1 == 0: break tdata2 = self.gdb.p("((%s *)&data)[%d]" % (xlen_type, 2*i+1)) if tdata1 & dmode: dmode_count += 1 else: assertEqual(tdata1 & 0xffff, tdata1_lsbs) assertEqual(tdata2, tdata2) assertGreater(i, 1) assertEqual(dmode_count, 1) return triggers def test(self): # If we want this test to run from flash, we can't have any software # breakpoints set. self.gdb.command("hbreak write_load_trigger") self.gdb.p("$pc=write_store_trigger") output = self.gdb.c() assertIn("write_load_trigger", output) self.check_triggers((1<<6) | (1<<1), 0xdeadbee0) self.gdb.command("delete") self.gdb.command("hbreak clear_triggers") output = self.gdb.c() assertIn("clear_triggers", output) self.check_triggers((1<<6) | (1<<0), 0xfeedac00) self.gdb.command("delete") self.exit() class RegsTest(GdbSingleHartTest): compile_args = ("programs/regs.S", ) def setup(self): self.gdb.load() main_bp = self.gdb.b("main") output = self.gdb.c() assertIn("Breakpoint ", output) assertIn("main", output) self.gdb.command("delete %d" % main_bp) self.gdb.b("handle_trap") class WriteGprs(RegsTest): def test(self): regs = [("x%d" % n) for n in range(2, 32)] self.gdb.p("$pc=write_regs") for i, r in enumerate(regs): self.gdb.p("$%s=%d" % (r, (0xdeadbeef<\n") self.download_c.write( "unsigned int crc32a(uint8_t *message, unsigned int size);\n") self.download_c.write("uint32_t length = %d;\n" % length) self.download_c.write("uint8_t d[%d] = {\n" % length) self.crc = 0 assert length % 16 == 0 for i in range(length / 16): self.download_c.write(" /* 0x%04x */ " % (i * 16)) for _ in range(16): value = random.randrange(1<<8) self.download_c.write("0x%02x, " % value) self.crc = binascii.crc32("%c" % value, self.crc) self.download_c.write("\n") self.download_c.write("};\n") self.download_c.write("uint8_t *data = &d[0];\n") self.download_c.write( "uint32_t main() { return crc32a(data, length); }\n") self.download_c.flush() if self.crc < 0: self.crc += 2**32 self.binary = self.target.compile(self.hart, self.download_c.name, "programs/checksum.c") self.gdb.global_command("file %s" % self.binary) def test(self): self.gdb.load() self.parkOtherHarts() self.gdb.command("b _exit") self.gdb.c(ops=100) assertEqual(self.gdb.p("status"), self.crc) os.unlink(self.download_c.name) #class MprvTest(GdbSingleHartTest): # compile_args = ("programs/mprv.S", ) # def setup(self): # self.gdb.load() # # def test(self): # """Test that the debugger can access memory when MPRV is set.""" # self.gdb.c(wait=False) # time.sleep(0.5) # self.gdb.interrupt() # output = self.gdb.command("p/x *(int*)(((char*)&data)-0x80000000)") # assertIn("0xbead", output) class PrivTest(GdbSingleHartTest): compile_args = ("programs/priv.S", ) def setup(self): # pylint: disable=attribute-defined-outside-init self.gdb.load() misa = self.hart.misa self.supported = set() if misa & (1<<20): self.supported.add(0) if misa & (1<<18): self.supported.add(1) if misa & (1<<7): self.supported.add(2) self.supported.add(3) # Disable physical memory protection by allowing U mode access to all # memory. try: self.gdb.p("$pmpcfg0=0xf") # TOR, R, W, X self.gdb.p("$pmpaddr0=0x%x" % ((self.hart.ram + self.hart.ram_size) >> 2)) except testlib.CouldNotFetch: # PMP registers are optional pass # Ensure Virtual Memory is disabled if applicable (SATP register is not # reset) try: self.gdb.p("$satp=0") except testlib.CouldNotFetch: # SATP only exists if you have S mode. pass class PrivRw(PrivTest): def test(self): """Test reading/writing priv.""" # Leave the PC at _start, where the first 4 instructions should be # legal in any mode. for privilege in range(4): self.gdb.p("$priv=%d" % privilege) self.gdb.stepi() actual = self.gdb.p("$priv") assertIn(actual, self.supported) if privilege in self.supported: assertEqual(actual, privilege) class PrivChange(PrivTest): def test(self): """Test that the core's privilege level actually changes.""" if 0 not in self.supported: return 'not_applicable' self.gdb.b("main") self.gdb.c() # Machine mode self.gdb.p("$priv=3") main_address = self.gdb.p("$pc") self.gdb.stepi() assertEqual("%x" % self.gdb.p("$pc"), "%x" % (main_address+4)) # User mode self.gdb.p("$priv=0") self.gdb.stepi() # Should have taken an exception, so be nowhere near main. pc = self.gdb.p("$pc") assertTrue(pc < main_address or pc > main_address + 0x100) parsed = None def main(): parser = argparse.ArgumentParser( description="Test that gdb can talk to a RISC-V target.", epilog=""" Example command line from the real world: Run all RegsTest cases against a physical FPGA, with custom openocd command: ./gdbserver.py --freedom-e300 --server_cmd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl -d" Simple """) targets.add_target_options(parser) testlib.add_test_run_options(parser) # TODO: remove global global parsed # pylint: disable=global-statement parsed = parser.parse_args() target = targets.target(parsed) testlib.print_log_names = parsed.print_log_names module = sys.modules[__name__] return testlib.run_all_tests(module, target, parsed) # TROUBLESHOOTING TIPS # If a particular test fails, run just that one test, eg.: # ./gdbserver.py MprvTest.test_mprv # Then inspect gdb.log and spike.log to see what happened in more detail. if __name__ == '__main__': sys.exit(main())