From a1d0969cd730d80d5a2d340d63fb3d7e56cd2339 Mon Sep 17 00:00:00 2001
From: John Ingalls <43973001+ingallsj@users.noreply.github.com>
Date: Mon, 26 Sep 2022 15:15:08 -0700
Subject: zicbo test zero (#411)

---
 isa/Makefile            |  6 ++++--
 isa/rv64mzicbo/Makefrag |  8 ++++++++
 isa/rv64mzicbo/zero.S   | 37 +++++++++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+), 2 deletions(-)
 create mode 100644 isa/rv64mzicbo/Makefrag
 create mode 100644 isa/rv64mzicbo/zero.S

(limited to 'isa')

diff --git a/isa/Makefile b/isa/Makefile
index 681f322..0203a82 100644
--- a/isa/Makefile
+++ b/isa/Makefile
@@ -17,6 +17,7 @@ include $(src_dir)/rv64uzfh/Makefrag
 include $(src_dir)/rv64si/Makefrag
 include $(src_dir)/rv64ssvnapot/Makefrag
 include $(src_dir)/rv64mi/Makefrag
+include $(src_dir)/rv64mzicbo/Makefrag
 endif
 include $(src_dir)/rv32ui/Makefrag
 include $(src_dir)/rv32uc/Makefrag
@@ -49,10 +50,10 @@ vpath %.S $(src_dir)
 	$(RISCV_OBJDUMP) $< > $@
 
 %.out: %
-	$(RISCV_SIM) --isa=rv64gc_zfh_svnapot $< 2> $@
+	$(RISCV_SIM) --isa=rv64gc_zfh_zicboz_svnapot $< 2> $@
 
 %.out32: %
-	$(RISCV_SIM) --isa=rv32gc_zfh_svnapot $< 2> $@
+	$(RISCV_SIM) --isa=rv32gc_zfh_zicboz_svnapot $< 2> $@
 
 define compile_template
 
@@ -95,6 +96,7 @@ $(eval $(call compile_template,rv64ua,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uf,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ud,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64uzfh,-march=rv64g_zfh -mabi=lp64))
+$(eval $(call compile_template,rv64mzicbo,-march=rv64g_zicboz -mabi=lp64))
 $(eval $(call compile_template,rv64si,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64ssvnapot,-march=rv64g -mabi=lp64))
 $(eval $(call compile_template,rv64mi,-march=rv64g -mabi=lp64))
diff --git a/isa/rv64mzicbo/Makefrag b/isa/rv64mzicbo/Makefrag
new file mode 100644
index 0000000..a002cc9
--- /dev/null
+++ b/isa/rv64mzicbo/Makefrag
@@ -0,0 +1,8 @@
+#=======================================================================
+# Makefrag for rv64mzicbo tests
+#-----------------------------------------------------------------------
+
+rv64mzicbo_sc_tests = \
+	zero \
+
+rv64mzicbo_p_tests = $(addprefix rv64mzicbo-p-, $(rv64mzicbo_sc_tests))
diff --git a/isa/rv64mzicbo/zero.S b/isa/rv64mzicbo/zero.S
new file mode 100644
index 0000000..44448b0
--- /dev/null
+++ b/isa/rv64mzicbo/zero.S
@@ -0,0 +1,37 @@
+#*****************************************************************************
+#-----------------------------------------------------------------------------
+#
+# Test CBO.ZERO instruction.
+#
+
+#include "riscv_test.h"
+#include "test_macros.h"
+
+RVTEST_RV64M
+RVTEST_CODE_BEGIN
+
+  la  x1, tdat
+  .word 0x0040A00F  ; cbo.zero(x1)
+  TEST_LD_OP( 1, ld, 0, 0,  tdat )
+  TEST_LD_OP( 2, ld, 0, 8,  tdat )
+  TEST_LD_OP( 3, ld, 0, 16, tdat )
+  TEST_LD_OP( 4, ld, 0, 24, tdat )
+  TEST_LD_OP( 5, ld, 0, 32, tdat )
+  TEST_LD_OP( 6, ld, 0, 40, tdat )
+  TEST_LD_OP( 7, ld, 0, 48, tdat )
+  TEST_LD_OP( 8, ld, 0, 56, tdat )
+
+  j pass
+
+  TEST_PASSFAIL
+
+RVTEST_CODE_END
+
+  .data
+RVTEST_DATA_BEGIN
+
+  TEST_DATA
+
+tdat:  .dword 0xdeadbeefdeadbeef
+
+RVTEST_DATA_END
-- 
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