From 62a1beccc7a65f982af4a49be5300617b694f5b2 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Thu, 2 Jun 2022 11:08:30 -0700
Subject: Add unaligned test cases for lw

The test passes if either the target register contains the correct
value, or the target raises a misaligned load exception.
---
 isa/rv64ui/lw.S | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'isa')

diff --git a/isa/rv64ui/lw.S b/isa/rv64ui/lw.S
index 40a73f1..bb1cbb4 100644
--- a/isa/rv64ui/lw.S
+++ b/isa/rv64ui/lw.S
@@ -74,8 +74,31 @@ RVTEST_CODE_BEGIN
     li  x2, 2; \
   )
 
+  # Test unaligned accesses, if the target supports them.
+  # Assume little-endian
+  TEST_LD_OP( 1000, lw, 0x0000000000ff00ff, 0,  tdat );
+  TEST_LD_OP( 1001, lw, 0x000000000000ff00, 1,  tdat );
+  TEST_LD_OP( 1002, lw, 0xffffffffff0000ff, 2,  tdat );
+  TEST_LD_OP( 1003, lw, 0x0000000000ff0000, 3,  tdat );
+
+skip_unaligned_tests:
   TEST_PASSFAIL
 
+  .align 2
+  .global mtvec_handler
+mtvec_handler:
+  # Only unaligned access tests should trap
+  li t0, 1000
+  blt TESTNUM, t0, fail
+
+  li t0, CAUSE_MISALIGNED_LOAD
+  csrr t1, mcause
+  bne t0, t1, fail
+
+  la t0, skip_unaligned_tests
+  csrw mepc, t0
+  mret
+
 RVTEST_CODE_END
 
   .data
-- 
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