From 1b2c3ea84a7f8d8a833fca4d2b9aebb7d1ba4269 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Tue, 1 Jun 2021 23:52:43 -0700
Subject: Enable access to cycle counter before trying to write it

There are two reasons that writing the cycle counter might trap:
- Because it's a read-only CSR
- Because mcounteren.CY=0 or scounteren.CY=0

We want to make sure we're testing the first property, so set up
the other bits accordingly.
---
 isa/rv64si/csr.S | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'isa')

diff --git a/isa/rv64si/csr.S b/isa/rv64si/csr.S
index 9bb4ea5..0ba1e1f 100644
--- a/isa/rv64si/csr.S
+++ b/isa/rv64si/csr.S
@@ -95,6 +95,19 @@ RVTEST_CODE_BEGIN
   srli a0, a0, 20 # a0 = a0 >> 20
   andi a0, a0, 1  # a0 = a0 & 1
   beqz a0, finish # if no user mode, skip the rest of these checks
+
+  # Enable access to the cycle counter
+  csrwi mcounteren, 1
+
+  # Figure out if 'S' is set in misa
+  csrr a0, misa   # a0 = csr(misa)
+  srli a0, a0, 18 # a0 = a0 >> 20
+  andi a0, a0, 1  # a0 = a0 & 1
+  beqz a0, 1f
+
+  # Enable access to the cycle counter
+  csrwi scounteren, 1
+1:
 #endif /* __MACHINE_MODE */
 
   # jump to user land
-- 
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