From 5fe2ce69dcd1d0ddb42c4edffac7ab11d939ca45 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 23 Aug 2013 20:02:02 -0700 Subject: Reflect changes to ISA Conflicts: isa/Makefile --- env/p/riscv_test.h | 75 +++++++++++++++++++++++-------- env/pcr.h | 124 ++++++++++++++++++++++++++++++++++++++++++++++++++++ env/pm/riscv_test.h | 72 ++---------------------------- env/pt/riscv_test.h | 77 +++++--------------------------- env/v/entry.S | 44 +++++++++---------- env/v/pcr.h | 93 --------------------------------------- env/v/riscv_test.h | 23 +++------- env/v/vm.c | 20 ++++----- 8 files changed, 234 insertions(+), 294 deletions(-) create mode 100644 env/pcr.h delete mode 100644 env/v/pcr.h (limited to 'env') diff --git a/env/p/riscv_test.h b/env/p/riscv_test.h index a537fb2..08af9dc 100644 --- a/env/p/riscv_test.h +++ b/env/p/riscv_test.h @@ -1,44 +1,81 @@ #ifndef _ENV_PHYSICAL_SINGLE_CORE_H #define _ENV_PHYSICAL_SINGLE_CORE_H +#include "../pcr.h" + //----------------------------------------------------------------------- // Begin Macro //----------------------------------------------------------------------- #define RVTEST_RV64U \ + .macro init; \ + .endm #define RVTEST_RV64UF \ - RVTEST_RV64U; \ - RVTEST_FP_ENABLE + .macro init; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV64UV \ + .macro init; \ + RVTEST_FP_ENABLE; \ + RVTEST_VEC_ENABLE; \ + .endm #define RVTEST_RV32U \ - clearpcr cr0, 0x80 + .macro init; \ + RVTEST_32_ENABLE; \ + .endm + +#define RVTEST_RV32UF \ + .macro init; \ + RVTEST_32_ENABLE; \ + RVTEST_FP_ENABLE; \ + .endm + +#define RVTEST_RV32UV \ + .macro init; \ + RVTEST_32_ENABLE; \ + RVTEST_FP_ENABLE; \ + RVTEST_VEC_ENABLE; \ + .endm #define RVTEST_RV64S \ + .macro init; \ + .endm + +#define RVTEST_32_ENABLE \ + clearpcr status, SR_S64 \ #define RVTEST_FP_ENABLE \ - setpcr cr0, 2; \ - mfpcr a0, cr0; \ - and a0, a0, 2; \ + setpcr status, SR_EF; \ + mfpcr a0, status; \ + and a0, a0, SR_EF; \ bnez a0, 2f; \ RVTEST_PASS; \ -2:mtfsr x0; \ +2:fssr x0; \ #define RVTEST_VEC_ENABLE \ - mfpcr a0, cr0; \ - ori a0, a0, 4; \ - mtpcr a0, cr0; \ - li a0, 0xff; \ - mtpcr a0, cr18; \ + setpcr status, SR_EV; \ + mfpcr a0, status; \ + and a0, a0, SR_EV; \ + bnez a0, 2f; \ + RVTEST_PASS; \ +2: \ + +#define RISCV_MULTICORE_DISABLE \ + mfpcr a0, hartid; 1: bnez a0, 1b; \ + +#define EXTRA_INIT #define RVTEST_CODE_BEGIN \ .text; \ .align 4; \ .global _start; \ _start: \ - RVTEST_FP_ENABLE \ - RVTEST_VEC_ENABLE \ - mfpcr a0, cr10; 1: bnez a0, 1b; \ + RISCV_MULTICORE_DISABLE; \ + init; \ + EXTRA_INIT; \ //----------------------------------------------------------------------- // End Macro @@ -53,7 +90,7 @@ _start: \ #define RVTEST_PASS \ fence; \ li x1, 1; \ - mtpcr x1, cr30; \ + mtpcr x1, tohost; \ 1: b 1b; \ #define RVTEST_FAIL \ @@ -61,16 +98,18 @@ _start: \ beqz x28, 1f; \ sll x28, x28, 1; \ or x28, x28, 1; \ - mtpcr x28, cr30; \ + mtpcr x28, tohost; \ 1: b 1b; \ //----------------------------------------------------------------------- // Data Section Macro //----------------------------------------------------------------------- -#define RVTEST_DATA_BEGIN +#define RVTEST_DATA_BEGIN EXTRA_DATA #define RVTEST_DATA_END +#define EXTRA_DATA + //#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature: //#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: diff --git a/env/pcr.h b/env/pcr.h new file mode 100644 index 0000000..8780cdd --- /dev/null +++ b/env/pcr.h @@ -0,0 +1,124 @@ +// See LICENSE for license details. + +#ifndef _RISCV_PCR_H +#define _RISCV_PCR_H + +#define SR_S 0x00000001 +#define SR_PS 0x00000002 +#define SR_EI 0x00000004 +#define SR_PEI 0x00000008 +#define SR_EF 0x00000010 +#define SR_U64 0x00000020 +#define SR_S64 0x00000040 +#define SR_VM 0x00000080 +#define SR_EV 0x00000100 +#define SR_IM 0x00FF0000 +#define SR_IP 0xFF000000 +#define SR_ZERO ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP) +#define SR_IM_SHIFT 16 +#define SR_IP_SHIFT 24 + +#define PCR_SUP0 0 +#define PCR_SUP1 1 +#define PCR_EPC 2 +#define PCR_BADVADDR 3 +#define PCR_PTBR 4 +#define PCR_ASID 5 +#define PCR_COUNT 6 +#define PCR_COMPARE 7 +#define PCR_EVEC 8 +#define PCR_CAUSE 9 +#define PCR_SR 10 +#define PCR_HARTID 11 +#define PCR_IMPL 12 +#define PCR_FATC 13 +#define PCR_SEND_IPI 14 +#define PCR_CLR_IPI 15 +#define PCR_VECBANK 18 +#define PCR_VECCFG 19 +#define PCR_RESET 29 +#define PCR_TOHOST 30 +#define PCR_FROMHOST 31 + +#define IRQ_COP 2 +#define IRQ_IPI 5 +#define IRQ_HOST 6 +#define IRQ_TIMER 7 + +#define IMPL_SPIKE 1 +#define IMPL_ROCKET 2 + +#define CAUSE_MISALIGNED_FETCH 0 +#define CAUSE_FAULT_FETCH 1 +#define CAUSE_ILLEGAL_INSTRUCTION 2 +#define CAUSE_PRIVILEGED_INSTRUCTION 3 +#define CAUSE_FP_DISABLED 4 +#define CAUSE_SYSCALL 6 +#define CAUSE_BREAKPOINT 7 +#define CAUSE_MISALIGNED_LOAD 8 +#define CAUSE_MISALIGNED_STORE 9 +#define CAUSE_FAULT_LOAD 10 +#define CAUSE_FAULT_STORE 11 +#define CAUSE_VECTOR_DISABLED 12 +#define CAUSE_VECTOR_BANK 13 + +#define CAUSE_VECTOR_MISALIGNED_FETCH 24 +#define CAUSE_VECTOR_FAULT_FETCH 25 +#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26 +#define CAUSE_VECTOR_ILLEGAL_COMMAND 27 +#define CAUSE_VECTOR_MISALIGNED_LOAD 28 +#define CAUSE_VECTOR_MISALIGNED_STORE 29 +#define CAUSE_VECTOR_FAULT_LOAD 30 +#define CAUSE_VECTOR_FAULT_STORE 31 + +// page table entry (PTE) fields +#define PTE_V 0x001 // Entry is a page Table descriptor +#define PTE_T 0x002 // Entry is a page Table, not a terminal node +#define PTE_G 0x004 // Global +#define PTE_UR 0x008 // User Write permission +#define PTE_UW 0x010 // User Read permission +#define PTE_UX 0x020 // User eXecute permission +#define PTE_SR 0x040 // Supervisor Read permission +#define PTE_SW 0x080 // Supervisor Write permission +#define PTE_SX 0x100 // Supervisor eXecute permission +#define PTE_PERM (PTE_SR | PTE_SW | PTE_SX | PTE_UR | PTE_UW | PTE_UX) + +#ifdef __riscv + +#ifdef __riscv64 +# define RISCV_PGLEVELS 3 +# define RISCV_PGSHIFT 13 +#else +# define RISCV_PGLEVELS 2 +# define RISCV_PGSHIFT 12 +#endif +#define RISCV_PGLEVEL_BITS 10 +#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) + +#ifndef __ASSEMBLER__ + +#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \ + asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \ + __tmp2; }) + +#define mfpcr(reg) ({ long __tmp; \ + asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \ + __tmp; }) + +#define setpcr(reg,val) ({ long __tmp; \ + asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ + __tmp; }) + +#define clearpcr(reg,val) ({ long __tmp; \ + asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ + __tmp; }) + +#define rdcycle() ({ unsigned long __tmp; \ + asm volatile ("rdcycle %0" : "=r"(__tmp)); \ + __tmp; }) + +#endif + +#endif + +#endif diff --git a/env/pm/riscv_test.h b/env/pm/riscv_test.h index 98d0580..4bd1637 100644 --- a/env/pm/riscv_test.h +++ b/env/pm/riscv_test.h @@ -1,73 +1,9 @@ #ifndef _ENV_PHYSICAL_MULTI_CORE_H -#define _ENV_PHYSICAL_MULTI_CORE_H +#define _ENV_PHYSICAL_MULTI_CORE_HA -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- +#include "../p/riscv_test.h" -#define RVTEST_RV64U \ - -#define RVTEST_RV64UF \ - RVTEST_RV64U; \ - RVTEST_FP_ENABLE - -#define RVTEST_RV64S \ - -#define RVTEST_FP_ENABLE \ - setpcr cr0, 2; \ - mfpcr a0, cr0; \ - and a0, a0, 2; \ - bnez a0, 2f; \ - RVTEST_PASS; \ -2:mtfsr x0; \ - -#define RVTEST_VEC_ENABLE \ - mfpcr a0, cr0; \ - ori a0, a0, 4; \ - mtpcr a0, cr0; \ - li a0, 0xff; \ - mtpcr a0, cr18; \ - -#define RVTEST_CODE_BEGIN \ - .text; \ - .align 4; \ - .global _start; \ -_start: \ - RVTEST_FP_ENABLE \ - RVTEST_VEC_ENABLE \ - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END \ - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#define RVTEST_FAIL \ - fence; \ - beqz x28, 1f; \ - sll x28, x28, 1; \ - or x28, x28, 1; \ - mtpcr x28, cr30; \ -1: b 1b; \ - -#define RVTEST_PASS \ - fence; \ - li x1, 1; \ - mtpcr x1, cr30; \ -1: b 1b; \ - -//----------------------------------------------------------------------- -// Data Section Macro -//----------------------------------------------------------------------- - -#define RVTEST_DATA_BEGIN -#define RVTEST_DATA_END - -//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature: -//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: +#undef RISCV_MULTICORE_DISABLE +#define RISCV_MULTICORE_DISABLE #endif diff --git a/env/pt/riscv_test.h b/env/pt/riscv_test.h index 748fe97..822dcfa 100644 --- a/env/pt/riscv_test.h +++ b/env/pt/riscv_test.h @@ -1,74 +1,22 @@ #ifndef _ENV_PHYSICAL_SINGLE_CORE_TIMER_H #define _ENV_PHYSICAL_SINGLE_CORE_TIMER_H -#include "pcr.h" +#include "../p/riscv_test.h" -//----------------------------------------------------------------------- -// Begin Macro -//----------------------------------------------------------------------- - -#define RVTEST_RV64U \ - -#define RVTEST_RV64UF \ - RVTEST_RV64U; \ - RVTEST_FP_ENABLE - -#define RVTEST_FP_ENABLE \ - setpcr cr0, 2; \ - mfpcr a0, cr0; \ - and a0, a0, 2; \ - bnez a0, 2f; \ - RVTEST_PASS; \ -2:mtfsr x0; \ - -#define RVTEST_VEC_ENABLE \ - mfpcr a0, cr0; \ - ori a0, a0, 4; \ - mtpcr a0, cr0; \ - li a0, 0xff; \ - mtpcr a0, cr18; \ - -#define RVTEST_CODE_BEGIN \ - .text; \ - .align 4; \ - .global _start; \ -_start: \ - RVTEST_FP_ENABLE \ - RVTEST_VEC_ENABLE \ - mfpcr a0, cr10; 1: bnez a0, 1b; \ - ENABLE_TIMER_INTERRUPT \ - -//----------------------------------------------------------------------- -// End Macro -//----------------------------------------------------------------------- - -#define RVTEST_CODE_END \ - XCPT_HANDLER \ - -//----------------------------------------------------------------------- -// Pass/Fail Macro -//----------------------------------------------------------------------- - -#define RVTEST_PASS \ - fence; \ - li x1, 1; \ - mtpcr x1, cr30; \ -1: b 1b; \ - -#define RVTEST_FAIL \ - fence; \ - beqz x28, 1f; \ - sll x28, x28, 1; \ - or x28, x28, 1; \ - mtpcr x28, cr30; \ -1: b 1b; \ +#undef EXTRA_INIT +#define EXTRA_INIT \ + ENABLE_TIMER_INTERRUPT; \ + b 6f; \ + XCPT_HANDLER; \ +6: //----------------------------------------------------------------------- // Data Section Macro //----------------------------------------------------------------------- -#define RVTEST_DATA_BEGIN \ - .align 3; \ +#undef EXTRA_DATA +#define EXTRA_DATA \ + .align 3; \ regspill: \ .dword 0xdeadbeefcafebabe; \ .dword 0xdeadbeefcafebabe; \ @@ -128,11 +76,6 @@ evac: \ .dword 0xdeadbeefcafebabe; \ .dword 0xdeadbeefcafebabe; \ -#define RVTEST_DATA_END - -//#define RVTEST_DATA_BEGIN .align 4; .global begin_signature; begin_signature: -//#define RVTEST_DATA_END .align 4; .global end_signature; end_signature: - //----------------------------------------------------------------------- // Misc //----------------------------------------------------------------------- diff --git a/env/v/entry.S b/env/v/entry.S index 35eaae3..c3ac344 100644 --- a/env/v/entry.S +++ b/env/v/entry.S @@ -51,19 +51,19 @@ save_tf: # write the trap frame onto the stack STORE x30,30*REGBYTES(x2) STORE x31,31*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_K0) + mfpcr x3,sup0 STORE x3,1*REGBYTES(x2) # x1 is in PCR_K0 - mfpcr x3,ASM_CR(PCR_K1) + mfpcr x3,sup1 STORE x3,2*REGBYTES(x2) # x2 is in PCR_K1 # get sr, epc, badvaddr, cause - mfpcr x3,ASM_CR(PCR_SR) # sr + mfpcr x3,status # sr STORE x3,32*REGBYTES(x2) - mfpcr x4,ASM_CR(PCR_EPC) # epc + mfpcr x4,epc # epc STORE x4,33*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_BADVADDR) # badvaddr + mfpcr x3,badvaddr # badvaddr STORE x3,34*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_CAUSE) # cause + mfpcr x3,cause # cause STORE x3,35*REGBYTES(x2) # get faulting insn, if it wasn't a fetch-related trap @@ -77,10 +77,10 @@ save_tf: # write the trap frame onto the stack sh x4,2+36*REGBYTES(x2) 1: - mfpcr x3,ASM_CR(PCR_VECBANK) # vecbank - STORE x3,37*REGBYTES(x2) - mfpcr x3,ASM_CR(PCR_VECCFG) # veccfg - STORE x3,38*REGBYTES(x2) + #mfpcr x3,ASM_CR(PCR_VECBANK) # vecbank + #STORE x3,37*REGBYTES(x2) + #mfpcr x3,ASM_CR(PCR_VECCFG) # veccfg + #STORE x3,38*REGBYTES(x2) ret @@ -88,12 +88,12 @@ save_tf: # write the trap frame onto the stack pop_tf: # write the trap frame onto the stack # restore gprs LOAD a1,32*REGBYTES(a0) # restore sr (should disable interrupts) - mtpcr a1,ASM_CR(PCR_SR) + mtpcr a1,status LOAD x1,1*REGBYTES(a0) - mtpcr x1,ASM_CR(PCR_K0) + mtpcr x1,sup0 LOAD x1,2*REGBYTES(a0) - mtpcr x1,ASM_CR(PCR_K1) + mtpcr x1,sup1 move x1,a0 LOAD x3,3*REGBYTES(x1) LOAD x4,4*REGBYTES(x1) @@ -127,18 +127,18 @@ pop_tf: # write the trap frame onto the stack # gtfo! LOAD x2,33*REGBYTES(x1) - mtpcr x2,ASM_CR(PCR_EPC) - mfpcr x1,ASM_CR(PCR_K0) - mfpcr x2,ASM_CR(PCR_K1) + mtpcr x2,epc + mfpcr x1,sup0 + mfpcr x2,sup1 eret .global trap_entry trap_entry: - mtpcr ra,ASM_CR(PCR_K0) - mtpcr x2,ASM_CR(PCR_K1) + mtpcr ra,sup0 + mtpcr x2,sup1 # coming from kernel? - mfpcr ra,ASM_CR(PCR_SR) + mfpcr ra,status and ra,ra,SR_PS bnez ra, 1f @@ -146,9 +146,9 @@ trap_entry: la x2,stack_top+MAX_TEST_PAGES*PGSIZE-SIZEOF_TRAPFRAME_T jal save_tf move sp,x2 - setpcr ASM_CR(PCR_SR), SR_ET + setpcr status, SR_EI move a0,x2 - mfpcr ra,ASM_CR(PCR_SR) + mfpcr ra,status and ra,ra,SR_EV beqz ra, 2f addi x2,x2,39*REGBYTES @@ -159,7 +159,7 @@ trap_entry: 1:add x2, sp, -SIZEOF_TRAPFRAME_T jal save_tf move sp,x2 - setpcr ASM_CR(PCR_SR), SR_ET + setpcr status, SR_EI move a0,x2 jal handle_trap diff --git a/env/v/pcr.h b/env/v/pcr.h deleted file mode 100644 index 72043b7..0000000 --- a/env/v/pcr.h +++ /dev/null @@ -1,93 +0,0 @@ -#ifndef _RISCV_PCR_H -#define _RISCV_PCR_H - -#define SR_ET 0x00000001 -#define SR_EF 0x00000002 -#define SR_EV 0x00000004 -#define SR_EC 0x00000008 -#define SR_PS 0x00000010 -#define SR_S 0x00000020 -#define SR_U64 0x00000040 -#define SR_S64 0x00000080 -#define SR_VM 0x00000100 -#define SR_IM 0x00FF0000 -#define SR_ZERO ~(SR_ET|SR_EF|SR_EV|SR_EC|SR_PS|SR_S|SR_U64|SR_S64|SR_VM|SR_IM) -#define SR_IM_SHIFT 16 - -#define PCR_SR 0 -#define PCR_EPC 1 -#define PCR_BADVADDR 2 -#define PCR_EVEC 3 -#define PCR_COUNT 4 -#define PCR_COMPARE 5 -#define PCR_CAUSE 6 -#define PCR_PTBR 7 -#define PCR_SEND_IPI 8 -#define PCR_CLR_IPI 9 -#define PCR_COREID 10 -#define PCR_IMPL 11 -#define PCR_K0 12 -#define PCR_K1 13 -#define PCR_VECBANK 18 -#define PCR_VECCFG 19 -#define PCR_RESET 29 -#define PCR_TOHOST 30 -#define PCR_FROMHOST 31 - -#define IMPL_ISASIM 1 -#define IMPL_ROCKET 2 - -#define IRQ_IPI 5 -#define IRQ_TIMER 7 - -#define CAUSE_MISALIGNED_FETCH 0 -#define CAUSE_FAULT_FETCH 1 -#define CAUSE_ILLEGAL_INSTRUCTION 2 -#define CAUSE_PRIVILEGED_INSTRUCTION 3 -#define CAUSE_FP_DISABLED 4 -#define CAUSE_SYSCALL 6 -#define CAUSE_BREAKPOINT 7 -#define CAUSE_MISALIGNED_LOAD 8 -#define CAUSE_MISALIGNED_STORE 9 -#define CAUSE_FAULT_LOAD 10 -#define CAUSE_FAULT_STORE 11 -#define CAUSE_VECTOR_DISABLED 12 -#define CAUSE_VECTOR_BANK 13 - -#define CAUSE_VECTOR_MISALIGNED_FETCH 24 -#define CAUSE_VECTOR_FAULT_FETCH 25 -#define CAUSE_VECTOR_ILLEGAL_INSTRUCTION 26 -#define CAUSE_VECTOR_ILLEGAL_COMMAND 27 -#define CAUSE_VECTOR_MISALIGNED_LOAD 28 -#define CAUSE_VECTOR_MISALIGNED_STORE 29 -#define CAUSE_VECTOR_FAULT_LOAD 30 -#define CAUSE_VECTOR_FAULT_STORE 31 - -#ifdef __riscv - -#define ASM_CR(r) _ASM_CR(r) -#define _ASM_CR(r) cr##r - -#ifndef __ASSEMBLER__ - -#define mtpcr(reg,val) ({ long __tmp = (long)(val), __tmp2; \ - asm volatile ("mtpcr %0,%1,cr%2" : "=r"(__tmp2) : "r"(__tmp),"i"(reg)); \ - __tmp2; }) - -#define mfpcr(reg) ({ long __tmp; \ - asm volatile ("mfpcr %0,cr%1" : "=r"(__tmp) : "i"(reg)); \ - __tmp; }) - -#define setpcr(reg,val) ({ long __tmp; \ - asm volatile ("setpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#define clearpcr(reg,val) ({ long __tmp; \ - asm volatile ("clearpcr %0,cr%2,%1" : "=r"(__tmp) : "i"(val), "i"(reg)); \ - __tmp; }) - -#endif - -#endif - -#endif diff --git a/env/v/riscv_test.h b/env/v/riscv_test.h index 6aa232e..995db59 100644 --- a/env/v/riscv_test.h +++ b/env/v/riscv_test.h @@ -6,31 +6,22 @@ //----------------------------------------------------------------------- #define RVTEST_RV64U \ - .text; \ -init: \ - ret + .macro init; \ + .endm #define RVTEST_RV64UF \ - .text; \ -init: \ - mtfsr x0; \ - ret - -#define RVTEST_RV64S \ + .macro init; \ + fssr x0; \ + .endm #define RVTEST_VEC_ENABLE \ - mfpcr t0, cr0; \ - ori t0, t0, 4; \ - mtpcr t0, cr0; \ - li t0, 0xff; \ - mtpcr t0, cr11; \ #define RVTEST_CODE_BEGIN \ .text; \ .align 13; \ .global userstart; \ userstart: \ - jal init + init //----------------------------------------------------------------------- // End Macro @@ -59,7 +50,7 @@ userstart: \ // Supervisor mode definitions and macros //----------------------------------------------------------------------- -#include "pcr.h" +#include "../pcr.h" #define vvcfg(nxregs, nfregs) ({ \ asm volatile ("vvcfg %0,%1" : : "r"(nxregs), "r"(nfregs)); }) diff --git a/env/v/vm.c b/env/v/vm.c index 422eb8c..bd9c80e 100644 --- a/env/v/vm.c +++ b/env/v/vm.c @@ -89,8 +89,8 @@ void handle_fault(unsigned long addr) if (*RELOC(&freelist_head) == *RELOC(&freelist_tail)) *RELOC(&freelist_tail) = 0; - *RELOC(&l3pt[addr/PGSIZE]) = node->addr | 0x3F2; - mtpcr(PCR_PTBR, l1pt); + *RELOC(&l3pt[addr/PGSIZE]) = node->addr | PTE_UW | PTE_UR | PTE_UX | PTE_SW | PTE_SR | PTE_SX | PTE_V; + mtpcr(PCR_FATC, 0); assert(RELOC(&user_mapping[addr/PGSIZE])->addr == 0); *RELOC(&user_mapping[addr/PGSIZE]) = *node; @@ -186,10 +186,10 @@ void handle_trap(trapframe_t* tf) handle_fault(tf->epc); else if (tf->cause == CAUSE_ILLEGAL_INSTRUCTION) { - int mtfsr; - asm ("la %0, 1f; lw %0, 0(%0); b 2f; 1: mtfsr x0; 2:" : "=r"(mtfsr)); + int fssr; + asm ("la %0, 1f; lw %0, 0(%0); b 2f; 1: fssr x0; 2:" : "=r"(fssr)); - if (tf->insn == mtfsr) + if (tf->insn == fssr) terminate(1); // FP test on non-FP hardware. "succeed." else if ((tf->insn & 0xF83FFFFF) == 0x37B) emulate_vxcptsave(tf); @@ -214,7 +214,7 @@ out: void vm_boot(long test_addr, long seed) { - while (mfpcr(PCR_COREID) > 0); // only core 0 proceeds + while (mfpcr(PCR_HARTID) > 0); // only core 0 proceeds assert(SIZEOF_TRAPFRAME_T == sizeof(trapframe_t)); @@ -230,10 +230,10 @@ void vm_boot(long test_addr, long seed) freelist_nodes[MAX_TEST_PAGES-1].next = 0; assert(MAX_TEST_PAGES*2 < PTES_PER_PT); - l1pt[0] = (pte_t)l2pt | 1; - l2pt[0] = (pte_t)l3pt | 1; + l1pt[0] = (pte_t)l2pt | PTE_V | PTE_T; + l2pt[0] = (pte_t)l3pt | PTE_V | PTE_T; for (long i = 0; i < MAX_TEST_PAGES; i++) - l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | 0x382; + l3pt[i] = l3pt[i+MAX_TEST_PAGES] = (i*PGSIZE) | PTE_SW | PTE_SR | PTE_SX | PTE_V; mtpcr(PCR_PTBR, l1pt); mtpcr(PCR_SR, mfpcr(PCR_SR) | SR_VM | SR_EF); @@ -244,7 +244,7 @@ void vm_boot(long test_addr, long seed) asm volatile ("add sp, sp, %1; rdpc %0; addi %0, %0, 16; add %0, %0, %1; jr %0" : "=&r"(tmp) : "r"(adjustment)); memset(RELOC(&l3pt[0]), 0, MAX_TEST_PAGES*sizeof(pte_t)); - mtpcr(PCR_PTBR, l1pt); + mtpcr(PCR_FATC, 0); trapframe_t tf; memset(&tf, 0, sizeof(tf)); -- cgit v1.1