From 272e12eb177c662826f901d536f685a4abf62123 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Mon, 26 Jun 2017 10:00:34 -0700
Subject: Move target definition into individual files.

Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.

Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.
---
 debug/targets/RISC-V/spike32.cfg | 19 +++++++++++++++++++
 debug/targets/RISC-V/spike32.lds | 36 ++++++++++++++++++++++++++++++++++++
 debug/targets/RISC-V/spike32.py  | 12 ++++++++++++
 debug/targets/RISC-V/spike64.cfg | 19 +++++++++++++++++++
 debug/targets/RISC-V/spike64.lds | 34 ++++++++++++++++++++++++++++++++++
 debug/targets/RISC-V/spike64.py  | 12 ++++++++++++
 6 files changed, 132 insertions(+)
 create mode 100644 debug/targets/RISC-V/spike32.cfg
 create mode 100755 debug/targets/RISC-V/spike32.lds
 create mode 100644 debug/targets/RISC-V/spike32.py
 create mode 100644 debug/targets/RISC-V/spike64.cfg
 create mode 100755 debug/targets/RISC-V/spike64.lds
 create mode 100644 debug/targets/RISC-V/spike64.py

(limited to 'debug/targets/RISC-V')

diff --git a/debug/targets/RISC-V/spike32.cfg b/debug/targets/RISC-V/spike32.cfg
new file mode 100644
index 0000000..2742335
--- /dev/null
+++ b/debug/targets/RISC-V/spike32.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+
+init
+reset halt
+
+echo "Ready for Remote Connections"
diff --git a/debug/targets/RISC-V/spike32.lds b/debug/targets/RISC-V/spike32.lds
new file mode 100755
index 0000000..01d0e3d
--- /dev/null
+++ b/debug/targets/RISC-V/spike32.lds
@@ -0,0 +1,36 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  /* Leave some space for pk's data structures, which includes tohost/fromhost
+   * which are special addresses we ought to leave alone.  */
+  . = 0x10010000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/RISC-V/spike32.py b/debug/targets/RISC-V/spike32.py
new file mode 100644
index 0000000..3bf8b47
--- /dev/null
+++ b/debug/targets/RISC-V/spike32.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+class spike32(targets.Target):
+    xlen = 32
+    ram = 0x10000000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vector = 0x1000
+
+    def create(self):
+        return testlib.Spike(self)
diff --git a/debug/targets/RISC-V/spike64.cfg b/debug/targets/RISC-V/spike64.cfg
new file mode 100644
index 0000000..2742335
--- /dev/null
+++ b/debug/targets/RISC-V/spike64.cfg
@@ -0,0 +1,19 @@
+adapter_khz     10000
+
+interface remote_bitbang
+remote_bitbang_host $::env(REMOTE_BITBANG_HOST)
+remote_bitbang_port $::env(REMOTE_BITBANG_PORT)
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
+
+set _TARGETNAME $_CHIPNAME.cpu
+#target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+
+init
+reset halt
+
+echo "Ready for Remote Connections"
diff --git a/debug/targets/RISC-V/spike64.lds b/debug/targets/RISC-V/spike64.lds
new file mode 100755
index 0000000..dc7cb63
--- /dev/null
+++ b/debug/targets/RISC-V/spike64.lds
@@ -0,0 +1,34 @@
+OUTPUT_ARCH( "riscv" )
+
+SECTIONS
+{
+  . = 0x1212340000;
+  .text : 
+  {
+    *(.text.entry)
+    *(.text)
+  }
+
+  /* data segment */
+  .data : { *(.data) }
+
+  .sdata : {
+    __global_pointer$ = . + 0x800;
+    *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2)
+    *(.srodata*)
+    *(.sdata .sdata.* .gnu.linkonce.s.*)
+  }
+
+  /* bss segment */
+  .sbss : {
+    *(.sbss .sbss.* .gnu.linkonce.sb.*)
+    *(.scommon)
+  }
+  .bss : { *(.bss) }
+
+  __malloc_start = .;
+  . = . + 512;
+
+  /* End of uninitalized data segement */
+  _end = .;
+}
diff --git a/debug/targets/RISC-V/spike64.py b/debug/targets/RISC-V/spike64.py
new file mode 100644
index 0000000..c705857
--- /dev/null
+++ b/debug/targets/RISC-V/spike64.py
@@ -0,0 +1,12 @@
+import targets
+import testlib
+
+class spike64(targets.Target):
+    xlen = 64
+    ram = 0x1212340000
+    ram_size = 0x10000000
+    instruction_hardware_breakpoint_count = 4
+    reset_vector = 0x1000
+
+    def create(self):
+        return testlib.Spike(self)
-- 
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