From e06a435c1e545def71e833031356372f0828f165 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 24 Jun 2024 15:19:59 -0700 Subject: Use Zvl/Zve to communicate VLEN/ELEN to target in debug tests (#567) --- debug/test | Bin 0 -> 17704 bytes debug/testlib.py | 5 +++-- 2 files changed, 3 insertions(+), 2 deletions(-) create mode 100755 debug/test diff --git a/debug/test b/debug/test new file mode 100755 index 0000000..9b72737 Binary files /dev/null and b/debug/test differ diff --git a/debug/testlib.py b/debug/testlib.py index 1f107be..41d9cea 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -134,6 +134,9 @@ class Spike: else: isa = f"RV{self.harts[0].xlen}G" + if 'V' in isa[2:]: + isa += f"_Zvl{self.vlen}b_Zve{self.elen}d" + cmd += ["--isa", isa] cmd += ["--dm-auth"] @@ -159,8 +162,6 @@ class Spike: if not self.support_haltgroups: cmd.append("--dm-no-halt-groups") - if 'V' in isa[2:]: - cmd.append(f"--varch=vlen:{self.vlen},elen:{self.elen}") assert len(set(t.ram for t in self.harts)) == 1, \ "All spike harts must have the same RAM layout" -- cgit v1.1