From db31c3dd894bca1e7aed903a159cf0e794f177c0 Mon Sep 17 00:00:00 2001
From: Tim Newsome <tim@sifive.com>
Date: Tue, 27 Feb 2018 14:28:26 -0800
Subject: Test debug authentication.

Also halt instead of reset spike targets, which tests a more complicated
code path.
---
 debug/targets/RISC-V/spike-1.cfg    | 6 +++++-
 debug/targets/RISC-V/spike-2.cfg    | 9 ++++++++-
 debug/targets/RISC-V/spike-rtos.cfg | 6 +++++-
 debug/testlib.py                    | 1 +
 4 files changed, 19 insertions(+), 3 deletions(-)

diff --git a/debug/targets/RISC-V/spike-1.cfg b/debug/targets/RISC-V/spike-1.cfg
index fc20b53..eb9cfd7 100644
--- a/debug/targets/RISC-V/spike-1.cfg
+++ b/debug/targets/RISC-V/spike-1.cfg
@@ -13,4 +13,8 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 gdb_report_data_abort enable
 
 init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
diff --git a/debug/targets/RISC-V/spike-2.cfg b/debug/targets/RISC-V/spike-2.cfg
index 17526ec..e2bda12 100644
--- a/debug/targets/RISC-V/spike-2.cfg
+++ b/debug/targets/RISC-V/spike-2.cfg
@@ -16,4 +16,11 @@ target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1
 gdb_report_data_abort enable
 
 init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+targets $_TARGETNAME_0
+halt
+targets $_TARGETNAME_1
+halt
diff --git a/debug/targets/RISC-V/spike-rtos.cfg b/debug/targets/RISC-V/spike-rtos.cfg
index 799e3cb..79fc100 100644
--- a/debug/targets/RISC-V/spike-rtos.cfg
+++ b/debug/targets/RISC-V/spike-rtos.cfg
@@ -14,4 +14,8 @@ target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv
 gdb_report_data_abort enable
 
 init
-reset halt
+
+set challenge [ocd_riscv authdata_read]
+riscv authdata_write [expr $challenge + 1]
+
+halt
diff --git a/debug/testlib.py b/debug/testlib.py
index 3aaa542..735dcba 100644
--- a/debug/testlib.py
+++ b/debug/testlib.py
@@ -117,6 +117,7 @@ class Spike(object):
             isa = "RV%dG" % harts[0].xlen
 
         cmd += ["--isa", isa]
+        cmd += ["--debug-auth"]
 
         assert len(set(t.ram for t in harts)) == 1, \
                 "All spike harts must have the same RAM layout"
-- 
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