From 6fa1896b2a3f581359f0b6a952542f814e30602c Mon Sep 17 00:00:00 2001
From: Nils Asmussen <nils@os.inf.tu-dresden.de>
Date: Fri, 21 Feb 2020 21:24:50 +0100
Subject: scall: make the intention of the test in machine mode more clear
 (#246)

---
 isa/rv64si/scall.S | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 82f202a..77718f2 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -19,7 +19,6 @@ RVTEST_CODE_BEGIN
   #define scause mcause
   #define sepc mepc
   #define sret mret
-  #define stvec_handler mtvec_handler
   #undef SSTATUS_SPP
   #define SSTATUS_SPP MSTATUS_MPP
 #endif
@@ -57,6 +56,11 @@ do_scall:
 
   TEST_PASSFAIL
 
+# make the linker not find the symbol stvec_handler when running in machine
+# mode. env/p/riscv_test.h sets stvec to the address of that symbol in case it
+# is non-zero. thus, effectively, we don't register a handler for scalls, so
+# that the default handler (trap_vector) is used.
+#ifndef __MACHINE_MODE
   .align 2
   .global stvec_handler
 stvec_handler:
@@ -66,6 +70,7 @@ stvec_handler:
   csrr t0, sepc
   bne t0, t2, fail
   j pass
+#endif
 
 RVTEST_CODE_END
 
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