From 654a7a4a85918b73de6e301d7220a6e09bb6587a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 10 Jun 2016 14:30:58 -0700 Subject: Test more than one breakpoint at a time, if present --- isa/rv64mi/breakpoint.S | 112 +++++++++++++++++++++++++++++------------------- 1 file changed, 68 insertions(+), 44 deletions(-) diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 5e4dfbb..848435e 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -17,86 +17,109 @@ RVTEST_CODE_BEGIN li TESTNUM, 2 # Skip tdrselect is hard-wired. - li t0, 1<<(_RISCV_SZLONG-1) - csrw tdrselect, t0 - csrr t1, tdrselect - bne t0, t1, pass + li a0, 1<<(_RISCV_SZLONG-1) + csrw tdrselect, a0 + csrr a1, tdrselect + bne a0, a1, pass # Make sure there's a breakpoint there. - csrr t0, tdrdata1 - srli t0, t0, _RISCV_SZLONG-4 - li t1, 1 - bne t0, t1, pass - - la t2, 1f - csrw tdrdata2, t2 - li t0, BPCONTROL_M | BPCONTROL_X - csrw tdrdata1, t0 + csrr a0, tdrdata1 + srli a0, a0, _RISCV_SZLONG-4 + li a1, 1 + bne a0, a1, pass + + la a2, 1f + csrw tdrdata2, a2 + li a0, BPCONTROL_M | BPCONTROL_X + csrw tdrdata1, a0 # Skip if breakpoint type is unsupported. - csrr t1, tdrdata1 - andi t1, t1, 0x7ff - bne t0, t1, 2f + csrr a1, tdrdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f 1: # Trap handler should skip this instruction. j fail # Make sure reads don't trap. li TESTNUM, 3 - lw t0, (t2) + lw a0, (a2) 2: # Set up breakpoint to trap on M-mode reads. li TESTNUM, 4 - li t0, BPCONTROL_M | BPCONTROL_R - csrw tdrdata1, t0 + li a0, BPCONTROL_M | BPCONTROL_R + csrw tdrdata1, a0 # Skip if breakpoint type is unsupported. - csrr t1, tdrdata1 - andi t1, t1, 0x7ff - bne t0, t1, 2f - la t2, write_data - csrw tdrdata2, t2 + csrr a1, tdrdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + la a2, data1 + csrw tdrdata2, a2 # Trap handler should skip this instruction. - lw t2, (t2) - beqz t2, fail + lw a2, (a2) + beqz a2, fail # Make sure writes don't trap. li TESTNUM, 5 - sw x0, (t2) + sw x0, (a2) 2: # Set up breakpoint to trap on M-mode stores. li TESTNUM, 6 - li t0, BPCONTROL_M | BPCONTROL_W - csrw tdrdata1, t0 + li a0, BPCONTROL_M | BPCONTROL_W + csrw tdrdata1, a0 # Skip if breakpoint type is unsupported. - csrr t1, tdrdata1 - andi t1, t1, 0x7ff - bne t0, t1, 2f + csrr a1, tdrdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f # Trap handler should skip this instruction. - sw t2, (t2) + sw a2, (a2) # Make sure store didn't succeed. li TESTNUM, 7 - lw t2, (t2) - bnez t2, fail + lw a2, (a2) + bnez a2, fail + + # Try to set up a second breakpoint. + li a0, (1<<(_RISCV_SZLONG-1)) + 1 + csrw tdrselect, a0 + csrr a1, tdrselect + bne a0, a1, pass + li a0, BPCONTROL_M | BPCONTROL_R + csrw tdrdata1, a0 + la a3, data2 + csrw tdrdata2, a3 + + # Make sure the second breakpoint triggers. + li TESTNUM, 8 + lw a3, (a3) + beqz a3, fail + + # Make sure the first breakpoint still triggers. + li TESTNUM, 10 + la a2, data1 + sw a2, (a2) + li TESTNUM, 11 + lw a2, (a2) + bnez a2, fail 2: TEST_PASSFAIL mtvec_handler: # Only even-numbered tests should trap. - andi a0, TESTNUM, 1 - bnez a0, fail + andi t0, TESTNUM, 1 + bnez t0, fail - li a0, CAUSE_BREAKPOINT - csrr a1, mcause - bne a0, a1, fail + li t0, CAUSE_BREAKPOINT + csrr t1, mcause + bne t0, t1, fail - csrr a0, mepc - addi a0, a0, 4 - csrw mepc, a0 + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 mret RVTEST_CODE_END @@ -106,6 +129,7 @@ RVTEST_DATA_BEGIN TEST_DATA -write_data: .word 0 +data1: .word 0 +data2: .word 0 RVTEST_DATA_END -- cgit v1.1 From 190d9f8416b03a6b073d483ef181ee6fb3bad40d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Sebastian=20B=C3=B8e?= Date: Wed, 15 Jun 2016 02:17:16 +0200 Subject: rv32ui: sh: Added side effect test (#14) From the test comment: sh to a word aligned address should only affect the 2 lower bytes and should leave the 2 upper bytes unmodified. In this test we write 2 bytes to the lower 2 bytes of the word tdat11 and then ensure that the both the upper 2 bytes and lower 2 bytes are as expected. --- isa/rv32ui/sh.S | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/isa/rv32ui/sh.S b/isa/rv32ui/sh.S index 387e181..6c47274 100644 --- a/isa/rv32ui/sh.S +++ b/isa/rv32ui/sh.S @@ -68,6 +68,23 @@ RVTEST_CODE_BEGIN TEST_ST_SRC21_BYPASS( 22, 1, 1, lh, sh, 0x0011, 8, tdat ); TEST_ST_SRC21_BYPASS( 23, 2, 0, lh, sh, 0x3001, 10, tdat ); + #--------------------------------------------------------------- + # Side effect tests + #--------------------------------------------------------------- + + # sh to a word aligned address should only affect the 2 lower bytes + # and should leave the 2 upper bytes unmodified. + # + # In this test we write 2 bytes to the lower 2 bytes of the word + # tdat11 and then ensure that the both the upper 2 bytes and + # lower 2 bytes are as expected. + TEST_CASE( 24, x3, 0x12343098, \ + la x1, tdat11; \ + li x2, 0x00003098; \ + sh x2, 0(x1); \ + lw x3, 0(x1); \ + ) + li a0, 0xbeef la a1, tdat sh a0, 6(a1) @@ -92,5 +109,6 @@ tdat7: .half 0xbeef tdat8: .half 0xbeef tdat9: .half 0xbeef tdat10: .half 0xbeef +tdat11: .word 0x12345678 RVTEST_DATA_END -- cgit v1.1 From 0c4cfe09da4c66c70eec7de680c9612fe9aa3e4a Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 17 Jun 2016 21:00:02 -0700 Subject: bump env --- env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/env b/env index 4944be4..260b6ff 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 4944be4d45cafabce0519f223124d2934b9dcac5 +Subproject commit 260b6fff32036dcfc8299aa21dd7cd443b18bb6a -- cgit v1.1 From 26cfab585c781f06e977800000efe097dee4613d Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 17 Jun 2016 21:06:37 -0700 Subject: Fix breakpoint test when only one breakpoint present --- isa/rv64mi/breakpoint.S | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S index 848435e..77c9509 100644 --- a/isa/rv64mi/breakpoint.S +++ b/isa/rv64mi/breakpoint.S @@ -16,7 +16,7 @@ RVTEST_CODE_BEGIN # Set up breakpoint to trap on M-mode fetches. li TESTNUM, 2 - # Skip tdrselect is hard-wired. + # Skip tdrselect if hard-wired. li a0, 1<<(_RISCV_SZLONG-1) csrw tdrselect, a0 csrr a1, tdrselect @@ -87,6 +87,13 @@ RVTEST_CODE_BEGIN csrw tdrselect, a0 csrr a1, tdrselect bne a0, a1, pass + + # Make sure there's a breakpoint there. + csrr a0, tdrdata1 + srli a0, a0, _RISCV_SZLONG-4 + li a1, 1 + bne a0, a1, pass + li a0, BPCONTROL_M | BPCONTROL_R csrw tdrdata1, a0 la a3, data2 -- cgit v1.1 From b6b5e81217c1f2a70ecb6883b1756859cd7bb999 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 22 Jun 2016 15:37:33 -0700 Subject: split up rv64uf and rv64ud isa tests --- isa/Makefile | 2 + isa/rv64ud/Makefrag | 12 ++++++ isa/rv64ud/fadd.S | 44 +++++++++++++++++++++ isa/rv64ud/fclass.S | 44 +++++++++++++++++++++ isa/rv64ud/fcmp.S | 37 ++++++++++++++++++ isa/rv64ud/fcvt.S | 56 ++++++++++++++++++++++++++ isa/rv64ud/fcvt_w.S | 102 ++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv64ud/fdiv.S | 42 ++++++++++++++++++++ isa/rv64ud/fmadd.S | 45 +++++++++++++++++++++ isa/rv64ud/fmin.S | 43 ++++++++++++++++++++ isa/rv64ud/fsgnj.S | 44 +++++++++++++++++++++ isa/rv64ud/ldst.S | 38 ++++++++++++++++++ isa/rv64ud/move.S | 36 +++++++++++++++++ isa/rv64ud/recoding.S | 67 +++++++++++++++++++++++++++++++ isa/rv64ud/structural.S | 58 +++++++++++++++++++++++++++ isa/rv64uf/Makefrag | 2 +- isa/rv64uf/fadd.S | 29 ++++---------- isa/rv64uf/fclass.S | 17 +------- isa/rv64uf/fcmp.S | 2 +- isa/rv64uf/fcvt.S | 29 +------------- isa/rv64uf/fcvt_w.S | 91 ++++++++---------------------------------- isa/rv64uf/fdiv.S | 27 ++++--------- isa/rv64uf/fmadd.S | 34 +++++----------- isa/rv64uf/fmin.S | 16 +------- isa/rv64uf/fsgnj.S | 17 +------- isa/rv64uf/ldst.S | 2 - isa/rv64uf/move.S | 10 ++--- isa/rv64uf/recoding.S | 33 +++------------- isa/rv64uf/structural.S | 58 --------------------------- 29 files changed, 728 insertions(+), 309 deletions(-) create mode 100644 isa/rv64ud/Makefrag create mode 100644 isa/rv64ud/fadd.S create mode 100644 isa/rv64ud/fclass.S create mode 100644 isa/rv64ud/fcmp.S create mode 100644 isa/rv64ud/fcvt.S create mode 100644 isa/rv64ud/fcvt_w.S create mode 100644 isa/rv64ud/fdiv.S create mode 100644 isa/rv64ud/fmadd.S create mode 100644 isa/rv64ud/fmin.S create mode 100644 isa/rv64ud/fsgnj.S create mode 100644 isa/rv64ud/ldst.S create mode 100644 isa/rv64ud/move.S create mode 100644 isa/rv64ud/recoding.S create mode 100644 isa/rv64ud/structural.S delete mode 100644 isa/rv64uf/structural.S diff --git a/isa/Makefile b/isa/Makefile index 636cbbe..d07dfa6 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -6,6 +6,7 @@ src_dir := . include $(src_dir)/rv64ui/Makefrag include $(src_dir)/rv64uf/Makefrag +include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64mi/Makefrag include $(src_dir)/rv32ui/Makefrag @@ -66,6 +67,7 @@ $(eval $(call compile_template,rv32mi,-m32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui)) $(eval $(call compile_template,rv64uf)) +$(eval $(call compile_template,rv64ud)) $(eval $(call compile_template,rv64si)) $(eval $(call compile_template,rv64mi)) endif diff --git a/isa/rv64ud/Makefrag b/isa/rv64ud/Makefrag new file mode 100644 index 0000000..6e8be9c --- /dev/null +++ b/isa/rv64ud/Makefrag @@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv64ud tests +#----------------------------------------------------------------------- + +rv64ud_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \ + ldst move structural recoding \ + +rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) +rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) + +spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) diff --git a/isa/rv64ud/fadd.S b/isa/rv64ud/fadd.S new file mode 100644 index 0000000..4a314da --- /dev/null +++ b/isa/rv64ud/fadd.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_D(11, fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fclass.S b/isa/rv64ud/fclass.S new file mode 100644 index 0000000..3daace0 --- /dev/null +++ b/isa/rv64ud/fclass.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + #define TEST_FCLASS_D(testnum, correct, input) \ + TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ + fclass.d a0, fa0) + + TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) + TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) + TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) + TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) + TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) + TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) + TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) + TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) + TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) + TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcmp.S b/isa/rv64ud/fcmp.S new file mode 100644 index 0000000..173dc88 --- /dev/null +++ b/isa/rv64ud/fcmp.S @@ -0,0 +1,37 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_D( 2, feq.d, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 3, fle.d, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 4, flt.d, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_D( 5, feq.d, 0, -1.37, -1.36) + TEST_FP_CMP_OP_D( 6, fle.d, 1, -1.37, -1.36) + TEST_FP_CMP_OP_D( 7, flt.d, 1, -1.37, -1.36) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcvt.S b/isa/rv64ud/fcvt.S new file mode 100644 index 0000000..4f25d07 --- /dev/null +++ b/isa/rv64ud/fcvt.S @@ -0,0 +1,56 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2); + TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2); + + TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2); + TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2); + + TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); + TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); + + TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); + TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); + + TEST_FCVT_S_D(10, -1.5, -1.5) + TEST_FCVT_D_S(11, -1.5, -1.5) + + TEST_CASE(12, a0, 0x7ff8000000000000, + la a1, test_data_22; + ld a2, 0(a1); + fmv.d.x f2, a2; + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fmv.x.d a0, f2; + ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +test_data_22: + .dword 0x7ffcffffffff8004 + +RVTEST_DATA_END diff --git a/isa/rv64ud/fcvt_w.S b/isa/rv64ud/fcvt_w.S new file mode 100644 index 0000000..50e794c --- /dev/null +++ b/isa/rv64ud/fcvt_w.S @@ -0,0 +1,102 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); + + TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); + TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); + TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); + TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); + + TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); + + # test negative NaN, negative infinity conversion + TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) + TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) + TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) + TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) + + # test positive NaN, positive infinity conversion + TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) + TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) + TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) + TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) + + # test NaN, infinity conversions to unsigned integer + TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) + TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) + TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) + TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) + TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) + TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) + TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) + TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/isa/rv64ud/fdiv.S b/isa/rv64ud/fdiv.S new file mode 100644 index 0000000..8a9fd4d --- /dev/null +++ b/isa/rv64ud/fdiv.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); + + TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); + + TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); + + TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fmadd.S b/isa/rv64ud/fmadd.S new file mode 100644 index 0000000..7a69aad --- /dev/null +++ b/isa/rv64ud/fmadd.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fmin.S b/isa/rv64ud/fmin.S new file mode 100644 index 0000000..82641bc --- /dev/null +++ b/isa/rv64ud/fmin.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.d instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/fsgnj.S b/isa/rv64ud/fsgnj.S new file mode 100644 index 0000000..e914777 --- /dev/null +++ b/isa/rv64ud/fsgnj.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fsgnj.S +#----------------------------------------------------------------------------- +# +# Test fsgn{j|jn|x}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fsgnj.d, 0, -6.3, 6.3, -1.0 ); + TEST_FP_OP2_D( 3, fsgnj.d, 0, 7.3, 7.3, 2.0 ); + TEST_FP_OP2_D( 4, fsgnj.d, 0, -8.3, -8.3, -3.0 ); + TEST_FP_OP2_D( 5, fsgnj.d, 0, 9.3, -9.3, 4.0 ); + + TEST_FP_OP2_D(12, fsgnjn.d, 0, 6.3, 6.3, -1.0 ); + TEST_FP_OP2_D(13, fsgnjn.d, 0, -7.3, 7.3, 2.0 ); + TEST_FP_OP2_D(14, fsgnjn.d, 0, 8.3, -8.3, -3.0 ); + TEST_FP_OP2_D(15, fsgnjn.d, 0, -9.3, -9.3, 4.0 ); + + TEST_FP_OP2_D(22, fsgnjx.d, 0, -6.3, 6.3, -1.0 ); + TEST_FP_OP2_D(23, fsgnjx.d, 0, 7.3, 7.3, 2.0 ); + TEST_FP_OP2_D(24, fsgnjx.d, 0, 8.3, -8.3, -3.0 ); + TEST_FP_OP2_D(25, fsgnjx.d, 0, -9.3, -9.3, 4.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/ldst.S b/isa/rv64ud/ldst.S new file mode 100644 index 0000000..59084e3 --- /dev/null +++ b/isa/rv64ud/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/isa/rv64ud/move.S b/isa/rv64ud/move.S new file mode 100644 index 0000000..806d4de --- /dev/null +++ b/isa/rv64ud/move.S @@ -0,0 +1,36 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr, +# and fsgnj[x|n].d work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li a0, 1 +fssr a0 + + TEST_CASE(2, a1, 1, li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x34, frsr a0) + + TEST_CASE(5, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1) + TEST_CASE(6, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ud/recoding.S b/isa/rv64ud/recoding.S new file mode 100644 index 0000000..69ad665 --- /dev/null +++ b/isa/rv64ud/recoding.S @@ -0,0 +1,67 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + fld f0, minf, a0 + fld f1, three, a0 + fmul.d f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.d a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.d a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.d a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.d.w f0, x0 + li a0, 1 + fcvt.d.w f1, a0 + fmul.d f1, f1, f0 + TEST_CASE(5, a0, 1, feq.d a0, f0, f1) + TEST_CASE(6, a0, 1, fle.d a0, f0, f1) + TEST_CASE(7, a0, 0, flt.d a0, f0, f1) + + # When converting small doubles to single-precision subnormals, + # ensure that the extra precision is discarded. + flw f0, big, a0 + fld f1, tiny, a0 + fcvt.s.d f1, f1 + fmul.s f0, f0, f1 + fmv.x.s a0, f0 + lw a1, small + TEST_CASE(10, a0, 0, sub a0, a0, a1) + + # Make sure FSD+FLD correctly saves and restores a single-precision value. + flw f0, three, a0 + fadd.s f1, f0, f0 + fadd.s f0, f0, f0 + fsd f0, tiny, a0 + fld f0, tiny, a0 + TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .double -Inf +three: .double 3.0 +big: .float 1221 +small: .float 2.9133121e-37 +tiny: .double 2.3860049081905093e-40 + +RVTEST_DATA_END diff --git a/isa/rv64ud/structural.S b/isa/rv64ud/structural.S new file mode 100644 index 0000000..76c6691 --- /dev/null +++ b/isa/rv64ud/structural.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# structural.S +#----------------------------------------------------------------------------- +# +# This test verifies that the FPU correctly obviates structural hazards on its +# writeback port (e.g. fadd followed by fsgnj) +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li x25, 1 + +li x2, 0x3FF0000000000000 +li x1, 0x3F800000 + +#define TEST(nops, errcode) \ + fmv.d.x f4, x0 ;\ + fmv.s.x f3, x0 ;\ + fmv.d.x f2, x2 ;\ + fmv.s.x f1, x1 ;\ + j 1f ;\ + .align 5 ;\ +1:fmul.d f4, f2, f2 ;\ + nops ;\ + fsgnj.s f3, f1, f1 ;\ + fmv.x.d x4, f4 ;\ + fmv.x.s x3, f3 ;\ + beq x1, x3, 2f ;\ + RVTEST_FAIL ;\ +2:beq x2, x4, 2f ;\ + RVTEST_FAIL; \ +2:fmv.d.x f2, zero ;\ + fmv.s.x f1, zero ;\ + +TEST(;,2) +TEST(nop,4) +TEST(nop;nop,6) +TEST(nop;nop;nop,8) +TEST(nop;nop;nop;nop,10) +TEST(nop;nop;nop;nop;nop,12) +TEST(nop;nop;nop;nop;nop;nop,14) + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64uf/Makefrag b/isa/rv64uf/Makefrag index 978084a..d3c3f23 100644 --- a/isa/rv64uf/Makefrag +++ b/isa/rv64uf/Makefrag @@ -4,7 +4,7 @@ rv64uf_sc_tests = \ fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin fsgnj \ - ldst move structural recoding \ + ldst move recoding \ rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) diff --git a/isa/rv64uf/fadd.S b/isa/rv64uf/fadd.S index a5f3e42..800dc8c 100644 --- a/isa/rv64uf/fadd.S +++ b/isa/rv64uf/fadd.S @@ -4,7 +4,7 @@ # fadd.S #----------------------------------------------------------------------------- # -# Test f{add|sub|mul}.{s|d} instructions. +# Test f{add|sub|mul}.s instructions. # #include "riscv_test.h" @@ -21,29 +21,16 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D( 5, fadd.d, 0, 3.5, 2.5, 1.0 ); - TEST_FP_OP2_D( 6, fadd.d, 1, -1234, -1235.1, 1.1 ); - TEST_FP_OP2_D( 7, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_S(12, fsub.s, 0, 1.5, 2.5, 1.0 ); - TEST_FP_OP2_S(13, fsub.s, 1, -1234, -1235.1, -1.1 ); - TEST_FP_OP2_S(14, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_D(15, fsub.d, 0, 1.5, 2.5, 1.0 ); - TEST_FP_OP2_D(16, fsub.d, 1, -1234, -1235.1, -1.1 ); - TEST_FP_OP2_D(17, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_S(22, fmul.s, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_S(23, fmul.s, 1, 1358.61, -1235.1, -1.1 ); - TEST_FP_OP2_S(24, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); - - TEST_FP_OP2_D(25, fmul.d, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_D(26, fmul.d, 1, 1358.61, -1235.1, -1.1 ); - TEST_FP_OP2_D(27, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); # Is the canonical NaN generated for Inf - Inf? - TEST_FP_OP2_S(28, fsub.s, 0x10, 0f:7fc00000, Inf, Inf); - TEST_FP_OP2_D(29, fsub.d, 0x10, 0d:7ff8000000000000, Inf, Inf); + TEST_FP_OP2_S(11, fsub.s, 0x10, 0f:7fc00000, Inf, Inf); TEST_PASSFAIL diff --git a/isa/rv64uf/fclass.S b/isa/rv64uf/fclass.S index bcebbf8..5a6361e 100644 --- a/isa/rv64uf/fclass.S +++ b/isa/rv64uf/fclass.S @@ -4,7 +4,7 @@ # fclass.S #----------------------------------------------------------------------------- # -# Test fclass.{s|d} instructions. +# Test fclass.s instructions. # #include "riscv_test.h" @@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) - #define TEST_FCLASS_D(testnum, correct, input) \ - TEST_CASE(testnum, a0, correct, li a0, input; fmv.d.x fa0, a0; \ - fclass.d a0, fa0) - - TEST_FCLASS_D(12, 1 << 0, 0xfff0000000000000 ) - TEST_FCLASS_D(13, 1 << 1, 0xbff0000000000000 ) - TEST_FCLASS_D(14, 1 << 2, 0x800fffffffffffff ) - TEST_FCLASS_D(15, 1 << 3, 0x8000000000000000 ) - TEST_FCLASS_D(16, 1 << 4, 0x0000000000000000 ) - TEST_FCLASS_D(17, 1 << 5, 0x000fffffffffffff ) - TEST_FCLASS_D(18, 1 << 6, 0x3ff0000000000000 ) - TEST_FCLASS_D(19, 1 << 7, 0x7ff0000000000000 ) - TEST_FCLASS_D(20, 1 << 8, 0x7ff0000000000001 ) - TEST_FCLASS_D(21, 1 << 9, 0x7ff8000000000000 ) - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fcmp.S b/isa/rv64uf/fcmp.S index 252ad29..24b08c7 100644 --- a/isa/rv64uf/fcmp.S +++ b/isa/rv64uf/fcmp.S @@ -4,7 +4,7 @@ # fcmp.S #----------------------------------------------------------------------------- # -# Test f{eq|lt|le}.{s|d} instructions. +# Test f{eq|lt|le}.s instructions. # #include "riscv_test.h" diff --git a/isa/rv64uf/fcvt.S b/isa/rv64uf/fcvt.S index cbaf6d3..7bcb49a 100644 --- a/isa/rv64uf/fcvt.S +++ b/isa/rv64uf/fcvt.S @@ -4,7 +4,7 @@ # fcvt.S #----------------------------------------------------------------------------- # -# Test fcvt.{s|d}.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. # #include "riscv_test.h" @@ -29,30 +29,6 @@ RVTEST_CODE_BEGIN TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); - TEST_INT_FP_OP_D(12, fcvt.d.w, 2.0, 2); - TEST_INT_FP_OP_D(13, fcvt.d.w, -2.0, -2); - - TEST_INT_FP_OP_D(14, fcvt.d.wu, 2.0, 2); - TEST_INT_FP_OP_D(15, fcvt.d.wu, 4294967294, -2); - - TEST_INT_FP_OP_D(16, fcvt.d.l, 2.0, 2); - TEST_INT_FP_OP_D(17, fcvt.d.l, -2.0, -2); - - TEST_INT_FP_OP_D(18, fcvt.d.lu, 2.0, 2); - TEST_INT_FP_OP_D(19, fcvt.d.lu, 1.8446744073709552e19, -2); - - TEST_FCVT_S_D(20, -1.5, -1.5) - TEST_FCVT_D_S(21, -1.5, -1.5) - - TEST_CASE(22, a0, 0x7ff8000000000000, - la a1, test_data_22; - ld a2, 0(a1); - fmv.d.x f2, a2; - fcvt.s.d f2, f2; - fcvt.d.s f2, f2; - fmv.x.d a0, f2; - ) - TEST_PASSFAIL RVTEST_CODE_END @@ -62,7 +38,4 @@ RVTEST_DATA_BEGIN TEST_DATA -test_data_22: - .dword 0x7ffcffffffff8004 - RVTEST_DATA_END diff --git a/isa/rv64uf/fcvt_w.S b/isa/rv64uf/fcvt_w.S index 7b78eec..92faffa 100644 --- a/isa/rv64uf/fcvt_w.S +++ b/isa/rv64uf/fcvt_w.S @@ -4,7 +4,7 @@ # fcvt_w.S #----------------------------------------------------------------------------- # -# Test fcvt{wu|w|lu|l}.{s|d} instructions. +# Test fcvt{wu|w|lu|l}.s instructions. # #include "riscv_test.h" @@ -50,85 +50,28 @@ RVTEST_CODE_BEGIN TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz); TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(42, fcvt.w.d, 0x01, -1, -1.1, rtz); - TEST_FP_INT_OP_D(43, fcvt.w.d, 0x00, -1, -1.0, rtz); - TEST_FP_INT_OP_D(44, fcvt.w.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(45, fcvt.w.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(46, fcvt.w.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(47, fcvt.w.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(48, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); - TEST_FP_INT_OP_D(49, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); - - TEST_FP_INT_OP_D(52, fcvt.wu.d, 0x10, 0, -3.0, rtz); - TEST_FP_INT_OP_D(53, fcvt.wu.d, 0x10, 0, -1.0, rtz); - TEST_FP_INT_OP_D(54, fcvt.wu.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(55, fcvt.wu.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(56, fcvt.wu.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(57, fcvt.wu.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(58, fcvt.wu.d, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(59, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); - - TEST_FP_INT_OP_D(62, fcvt.l.d, 0x01, -1, -1.1, rtz); - TEST_FP_INT_OP_D(63, fcvt.l.d, 0x00, -1, -1.0, rtz); - TEST_FP_INT_OP_D(64, fcvt.l.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(65, fcvt.l.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(66, fcvt.l.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(67, fcvt.l.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(68, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); - TEST_FP_INT_OP_D(69, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); - TEST_FP_INT_OP_D(60, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); - TEST_FP_INT_OP_D(61, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); - - TEST_FP_INT_OP_D(72, fcvt.lu.d, 0x10, 0, -3.0, rtz); - TEST_FP_INT_OP_D(73, fcvt.lu.d, 0x10, 0, -1.0, rtz); - TEST_FP_INT_OP_D(74, fcvt.lu.d, 0x01, 0, -0.9, rtz); - TEST_FP_INT_OP_D(75, fcvt.lu.d, 0x01, 0, 0.9, rtz); - TEST_FP_INT_OP_D(76, fcvt.lu.d, 0x00, 1, 1.0, rtz); - TEST_FP_INT_OP_D(77, fcvt.lu.d, 0x01, 1, 1.1, rtz); - TEST_FP_INT_OP_D(78, fcvt.lu.d, 0x10, 0, -3e9, rtz); - TEST_FP_INT_OP_D(79, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); - # test negative NaN, negative infinity conversion - TEST_CASE( 80, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) - TEST_CASE( 81, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) - TEST_CASE( 82, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) - TEST_CASE( 83, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) - - TEST_CASE( 84, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) - TEST_CASE( 85, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) - TEST_CASE( 86, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) - TEST_CASE( 87, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) + TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) + TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) # test positive NaN, positive infinity conversion - TEST_CASE( 88, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) - TEST_CASE( 89, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) - TEST_CASE( 90, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) - TEST_CASE( 91, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) - - TEST_CASE( 92, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) - TEST_CASE( 93, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) - TEST_CASE( 94, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) - TEST_CASE( 95, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) + TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) + TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) # test NaN, infinity conversions to unsigned integer - TEST_CASE( 96, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) - TEST_CASE( 97, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) - TEST_CASE( 98, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) - TEST_CASE( 99, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) - TEST_CASE(100, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) - TEST_CASE(101, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) - TEST_CASE(102, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) - TEST_CASE(103, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) - TEST_CASE(104, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) - TEST_CASE(105, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) - TEST_CASE(106, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) - TEST_CASE(107, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) - TEST_CASE(108, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) - TEST_CASE(109, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) - TEST_CASE(110, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) - TEST_CASE(111, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fdiv.S b/isa/rv64uf/fdiv.S index 688f635..a75a23d 100644 --- a/isa/rv64uf/fdiv.S +++ b/isa/rv64uf/fdiv.S @@ -4,7 +4,7 @@ # fdiv.S #----------------------------------------------------------------------------- # -# Test f{div|sqrt}.{s|d} instructions. +# Test f{div|sqrt}.s instructions. # #include "riscv_test.h" @@ -17,27 +17,16 @@ RVTEST_CODE_BEGIN # Arithmetic tests #------------------------------------------------------------- - TEST_FP_OP2_S( 2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); - TEST_FP_OP2_S( 3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); - TEST_FP_OP2_S( 4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); + TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); - TEST_FP_OP2_D( 5, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); - TEST_FP_OP2_D( 6, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); - TEST_FP_OP2_D( 7, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); - TEST_FP_OP1_S(11, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); - TEST_FP_OP1_S(12, fsqrt.s, 0, 100, 10000 ); + TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); - TEST_FP_OP1_D(13, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); - TEST_FP_OP1_D(14, fsqrt.d, 0, 100, 10000 ); - - TEST_FP_OP1_S_DWORD_RESULT(15, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); - TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); - - TEST_FP_OP1_S(17, fsqrt.s, 1, 13.076696, 171.0); - TEST_FP_OP1_D(18, fsqrt.d, 1, 13.076696830622021, 171.0); - - TEST_FP_OP1_D(19, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); TEST_PASSFAIL diff --git a/isa/rv64uf/fmadd.S b/isa/rv64uf/fmadd.S index 62ea102..241bead 100644 --- a/isa/rv64uf/fmadd.S +++ b/isa/rv64uf/fmadd.S @@ -21,33 +21,17 @@ RVTEST_CODE_BEGIN TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 ); TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_D( 5, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D( 6, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D( 7, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_S( 8, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S( 9, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(10, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); - TEST_FP_OP3_D(11, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(12, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(13, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_S(14, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S(15, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(16, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_D(17, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(18, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(19, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_S(20, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_S(21, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_S(22, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); - - TEST_FP_OP3_D(23, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); - TEST_FP_OP3_D(24, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); - TEST_FP_OP3_D(25, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); TEST_PASSFAIL diff --git a/isa/rv64uf/fmin.S b/isa/rv64uf/fmin.S index 56a6e7b..a2650e5 100644 --- a/isa/rv64uf/fmin.S +++ b/isa/rv64uf/fmin.S @@ -4,7 +4,7 @@ # fmin.S #----------------------------------------------------------------------------- # -# Test f{min|max}.{s|d} instructinos. +# Test f{min|max}.s instructinos. # #include "riscv_test.h" @@ -31,20 +31,6 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); - TEST_FP_OP2_D(22, fmin.d, 0, 1.0, 2.5, 1.0 ); - TEST_FP_OP2_D(23, fmin.d, 0, -1235.1, -1235.1, 1.1 ); - TEST_FP_OP2_D(24, fmin.d, 0, -1235.1, 1.1, -1235.1 ); - TEST_FP_OP2_D(25, fmin.d, 0, -1235.1, NaN, -1235.1 ); - TEST_FP_OP2_D(26, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D(27, fmin.d, 0, -2.0, -1.0, -2.0 ); - - TEST_FP_OP2_D(32, fmax.d, 0, 2.5, 2.5, 1.0 ); - TEST_FP_OP2_D(33, fmax.d, 0, 1.1, -1235.1, 1.1 ); - TEST_FP_OP2_D(34, fmax.d, 0, 1.1, 1.1, -1235.1 ); - TEST_FP_OP2_D(35, fmax.d, 0, -1235.1, NaN, -1235.1 ); - TEST_FP_OP2_D(36, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); - TEST_FP_OP2_D(37, fmax.d, 0, -1.0, -1.0, -2.0 ); - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/fsgnj.S b/isa/rv64uf/fsgnj.S index 68d5ee6..6d4bdb4 100644 --- a/isa/rv64uf/fsgnj.S +++ b/isa/rv64uf/fsgnj.S @@ -4,7 +4,7 @@ # fsgnj.S #----------------------------------------------------------------------------- # -# Test fsgn{j|jn|x}.{s|d} instructions. +# Test fsgn{j|jn|x}.s instructions. # #include "riscv_test.h" @@ -32,21 +32,6 @@ RVTEST_CODE_BEGIN TEST_FP_OP2_S(24, fsgnjx.s, 0, 8.3, -8.3, -3.0 ); TEST_FP_OP2_S(25, fsgnjx.s, 0, -9.3, -9.3, 4.0 ); - TEST_FP_OP2_D(32, fsgnj.d, 0, -6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(33, fsgnj.d, 0, 7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(34, fsgnj.d, 0, -8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(35, fsgnj.d, 0, 9.3, -9.3, 4.0 ); - - TEST_FP_OP2_D(42, fsgnjn.d, 0, 6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(43, fsgnjn.d, 0, -7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(44, fsgnjn.d, 0, 8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(45, fsgnjn.d, 0, -9.3, -9.3, 4.0 ); - - TEST_FP_OP2_D(52, fsgnjx.d, 0, -6.3, 6.3, -1.0 ); - TEST_FP_OP2_D(53, fsgnjx.d, 0, 7.3, 7.3, 2.0 ); - TEST_FP_OP2_D(54, fsgnjx.d, 0, 8.3, -8.3, -3.0 ); - TEST_FP_OP2_D(55, fsgnjx.d, 0, -9.3, -9.3, 4.0 ); - TEST_PASSFAIL RVTEST_CODE_END diff --git a/isa/rv64uf/ldst.S b/isa/rv64uf/ldst.S index 63123f2..c35dd8d 100644 --- a/isa/rv64uf/ldst.S +++ b/isa/rv64uf/ldst.S @@ -15,8 +15,6 @@ RVTEST_CODE_BEGIN TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) - TEST_CASE(4, a0, 0x40000000bf800000, la a1, tdat; fld f2, 0(a1); fsd f2, 16(a1); ld a0, 16(a1)) - TEST_CASE(5, a0, 0xc080000040400000, la a1, tdat; fld f2, 8(a1); fsd f2, 16(a1); ld a0, 16(a1)) TEST_PASSFAIL diff --git a/isa/rv64uf/move.S b/isa/rv64uf/move.S index 53b8cf3..a94af55 100644 --- a/isa/rv64uf/move.S +++ b/isa/rv64uf/move.S @@ -5,7 +5,7 @@ #----------------------------------------------------------------------------- # # This test verifies that mxtf.[s,d], mftx.[s,d], fssr, frsr, -# and fsgnj[x|n].[s|d] work properly. +# and fsgnj[x|n].s work properly. # #include "riscv_test.h" @@ -22,12 +22,10 @@ fssr a0 TEST_CASE(4, a0, 0x34, frsr a0) TEST_CASE(5, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fmv.x.s a0, f0) - TEST_CASE(6, a0, 0x3FF02468A0000000, li a1, 0x3FF02468A0000000; fmv.d.x f1, a1; fmv.x.d a0, f1) - TEST_CASE(7, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(8, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(9, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1) - TEST_CASE(10, a0, 0xBFF02468A0001000, li a1, 0x3FF02468A0001000; li a2, -1; fmv.d.x f1, a1; fmv.d.x f2, a2; fsgnj.d f0, f1, f2; fmv.x.d a0, f0) + TEST_CASE(6, a0, 0xFFFFFFFFBF812345, li a1, 0xFFFFFFFFBF812345; fmv.s.x f0, a1; fsgnj.s f1, f0, f0; fmv.x.s a0, f1) + TEST_CASE(7, a0, 0x000000004BA98765, li a1, 0xFFFFFFFFCBA98765; fmv.s.x f0, a1; fsgnjx.s f1, f0, f0; fmv.x.s a0, f1) + TEST_CASE(8, a0, 0x000000005EADBEEF, li a1, 0xFFFFFFFFDEADBEEF; fmv.s.x f0, a1; fsgnjn.s f1, f0, f0; fmv.x.s a0, f1) TEST_PASSFAIL diff --git a/isa/rv64uf/recoding.S b/isa/rv64uf/recoding.S index 2ab17e2..802be66 100644 --- a/isa/rv64uf/recoding.S +++ b/isa/rv64uf/recoding.S @@ -25,31 +25,13 @@ RVTEST_CODE_BEGIN TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) # Likewise, but for zeroes. - fcvt.d.w f0, x0 + fcvt.s.w f0, x0 li a0, 1 - fcvt.d.w f1, a0 - fmul.d f1, f1, f0 - TEST_CASE(5, a0, 1, feq.d a0, f0, f1) - TEST_CASE(6, a0, 1, fle.d a0, f0, f1) - TEST_CASE(7, a0, 0, flt.d a0, f0, f1) - - # When converting small doubles to single-precision subnormals, - # ensure that the extra precision is discarded. - flw f0, big, a0 - fld f1, tiny, a0 - fcvt.s.d f1, f1 - fmul.s f0, f0, f1 - fmv.x.s a0, f0 - lw a1, small - TEST_CASE(10, a0, 0, sub a0, a0, a1) - - # Make sure FSD+FLD correctly saves and restores a single-precision value. - flw f0, three, a0 - fadd.s f1, f0, f0 - fadd.s f0, f0, f0 - fsd f0, tiny, a0 - fld f0, tiny, a0 - TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) TEST_PASSFAIL @@ -60,8 +42,5 @@ RVTEST_DATA_BEGIN minf: .float -Inf three: .float 3.0 -big: .float 1221 -small: .float 2.9133121e-37 -tiny: .double 2.3860049081905093e-40 RVTEST_DATA_END diff --git a/isa/rv64uf/structural.S b/isa/rv64uf/structural.S deleted file mode 100644 index 76c6691..0000000 --- a/isa/rv64uf/structural.S +++ /dev/null @@ -1,58 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# structural.S -#----------------------------------------------------------------------------- -# -# This test verifies that the FPU correctly obviates structural hazards on its -# writeback port (e.g. fadd followed by fsgnj) -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64UF -RVTEST_CODE_BEGIN - -li x25, 1 - -li x2, 0x3FF0000000000000 -li x1, 0x3F800000 - -#define TEST(nops, errcode) \ - fmv.d.x f4, x0 ;\ - fmv.s.x f3, x0 ;\ - fmv.d.x f2, x2 ;\ - fmv.s.x f1, x1 ;\ - j 1f ;\ - .align 5 ;\ -1:fmul.d f4, f2, f2 ;\ - nops ;\ - fsgnj.s f3, f1, f1 ;\ - fmv.x.d x4, f4 ;\ - fmv.x.s x3, f3 ;\ - beq x1, x3, 2f ;\ - RVTEST_FAIL ;\ -2:beq x2, x4, 2f ;\ - RVTEST_FAIL; \ -2:fmv.d.x f2, zero ;\ - fmv.s.x f1, zero ;\ - -TEST(;,2) -TEST(nop,4) -TEST(nop;nop,6) -TEST(nop;nop;nop,8) -TEST(nop;nop;nop;nop,10) -TEST(nop;nop;nop;nop;nop,12) -TEST(nop;nop;nop;nop;nop;nop,14) - -RVTEST_PASS - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END -- cgit v1.1 From 51671844c2588386ce3eacedf40d385e3c2b1484 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 22 Jun 2016 15:53:38 -0700 Subject: separate ua and um tests from ui tests --- isa/Makefile | 8 +++++ isa/rv32ua/Makefrag | 12 ++++++++ isa/rv32ua/amoadd_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoand_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amomax_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amomaxu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amomin_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amominu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv32ua/amoor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoswap_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/amoxor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv32ua/lrsc.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32ui/Makefrag | 5 --- isa/rv32ui/amoadd_w.S | 65 -------------------------------------- isa/rv32ui/amoand_w.S | 65 -------------------------------------- isa/rv32ui/amomax_w.S | 49 ----------------------------- isa/rv32ui/amomaxu_w.S | 49 ----------------------------- isa/rv32ui/amomin_w.S | 49 ----------------------------- isa/rv32ui/amominu_w.S | 49 ----------------------------- isa/rv32ui/amoor_w.S | 65 -------------------------------------- isa/rv32ui/amoswap_w.S | 65 -------------------------------------- isa/rv32ui/amoxor_w.S | 65 -------------------------------------- isa/rv32ui/div.S | 41 ------------------------ isa/rv32ui/divu.S | 41 ------------------------ isa/rv32ui/divuw.S | 41 ------------------------ isa/rv32ui/divw.S | 41 ------------------------ isa/rv32ui/lrsc.S | 84 -------------------------------------------------- isa/rv32ui/mul.S | 84 -------------------------------------------------- isa/rv32ui/mulh.S | 81 ------------------------------------------------ isa/rv32ui/mulhsu.S | 83 ------------------------------------------------- isa/rv32ui/mulhu.S | 82 ------------------------------------------------ isa/rv32ui/mulw.S | 72 ------------------------------------------- isa/rv32ui/rem.S | 41 ------------------------ isa/rv32ui/remu.S | 41 ------------------------ isa/rv32um/Makefrag | 13 ++++++++ isa/rv32um/div.S | 41 ++++++++++++++++++++++++ isa/rv32um/divu.S | 41 ++++++++++++++++++++++++ isa/rv32um/mul.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulh.S | 81 ++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulhsu.S | 83 +++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/mulhu.S | 82 ++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv32um/rem.S | 41 ++++++++++++++++++++++++ isa/rv32um/remu.S | 41 ++++++++++++++++++++++++ isa/rv64ua/Makefrag | 13 ++++++++ isa/rv64ua/amoadd_d.S | 64 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoadd_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoand_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoand_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amomax_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomax_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomaxu_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomaxu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomin_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amomin_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amominu_d.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amominu_w.S | 49 +++++++++++++++++++++++++++++ isa/rv64ua/amoor_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoswap_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoswap_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoxor_d.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/amoxor_w.S | 65 ++++++++++++++++++++++++++++++++++++++ isa/rv64ua/lrsc.S | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++ isa/rv64ui/Makefrag | 6 ---- isa/rv64ui/amoadd_d.S | 64 -------------------------------------- isa/rv64ui/amoadd_w.S | 65 -------------------------------------- isa/rv64ui/amoand_d.S | 65 -------------------------------------- isa/rv64ui/amoand_w.S | 65 -------------------------------------- isa/rv64ui/amomax_d.S | 49 ----------------------------- isa/rv64ui/amomax_w.S | 49 ----------------------------- isa/rv64ui/amomaxu_d.S | 49 ----------------------------- isa/rv64ui/amomaxu_w.S | 49 ----------------------------- isa/rv64ui/amomin_d.S | 49 ----------------------------- isa/rv64ui/amomin_w.S | 49 ----------------------------- isa/rv64ui/amominu_d.S | 49 ----------------------------- isa/rv64ui/amominu_w.S | 49 ----------------------------- isa/rv64ui/amoor_d.S | 65 -------------------------------------- isa/rv64ui/amoor_w.S | 65 -------------------------------------- isa/rv64ui/amoswap_d.S | 65 -------------------------------------- isa/rv64ui/amoswap_w.S | 65 -------------------------------------- isa/rv64ui/amoxor_d.S | 65 -------------------------------------- isa/rv64ui/amoxor_w.S | 65 -------------------------------------- isa/rv64ui/div.S | 41 ------------------------ isa/rv64ui/divu.S | 41 ------------------------ isa/rv64ui/divuw.S | 41 ------------------------ isa/rv64ui/divw.S | 41 ------------------------ isa/rv64ui/lrsc.S | 84 -------------------------------------------------- isa/rv64ui/mul.S | 78 ---------------------------------------------- isa/rv64ui/mulh.S | 72 ------------------------------------------- isa/rv64ui/mulhsu.S | 72 ------------------------------------------- isa/rv64ui/mulhu.S | 75 -------------------------------------------- isa/rv64ui/mulw.S | 72 ------------------------------------------- isa/rv64ui/rem.S | 41 ------------------------ isa/rv64ui/remu.S | 41 ------------------------ isa/rv64ui/remuw.S | 41 ------------------------ isa/rv64ui/remw.S | 42 ------------------------- isa/rv64um/Makefrag | 13 ++++++++ isa/rv64um/div.S | 41 ++++++++++++++++++++++++ isa/rv64um/divu.S | 41 ++++++++++++++++++++++++ isa/rv64um/divuw.S | 41 ++++++++++++++++++++++++ isa/rv64um/divw.S | 41 ++++++++++++++++++++++++ isa/rv64um/mul.S | 78 ++++++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulh.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulhsu.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulhu.S | 75 ++++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/mulw.S | 72 +++++++++++++++++++++++++++++++++++++++++++ isa/rv64um/rem.S | 41 ++++++++++++++++++++++++ isa/rv64um/remu.S | 41 ++++++++++++++++++++++++ isa/rv64um/remuw.S | 41 ++++++++++++++++++++++++ isa/rv64um/remw.S | 42 +++++++++++++++++++++++++ 110 files changed, 2981 insertions(+), 3087 deletions(-) create mode 100644 isa/rv32ua/Makefrag create mode 100644 isa/rv32ua/amoadd_w.S create mode 100644 isa/rv32ua/amoand_w.S create mode 100644 isa/rv32ua/amomax_w.S create mode 100644 isa/rv32ua/amomaxu_w.S create mode 100644 isa/rv32ua/amomin_w.S create mode 100644 isa/rv32ua/amominu_w.S create mode 100644 isa/rv32ua/amoor_w.S create mode 100644 isa/rv32ua/amoswap_w.S create mode 100644 isa/rv32ua/amoxor_w.S create mode 100644 isa/rv32ua/lrsc.S delete mode 100644 isa/rv32ui/amoadd_w.S delete mode 100644 isa/rv32ui/amoand_w.S delete mode 100644 isa/rv32ui/amomax_w.S delete mode 100644 isa/rv32ui/amomaxu_w.S delete mode 100644 isa/rv32ui/amomin_w.S delete mode 100644 isa/rv32ui/amominu_w.S delete mode 100644 isa/rv32ui/amoor_w.S delete mode 100644 isa/rv32ui/amoswap_w.S delete mode 100644 isa/rv32ui/amoxor_w.S delete mode 100644 isa/rv32ui/div.S delete mode 100644 isa/rv32ui/divu.S delete mode 100644 isa/rv32ui/divuw.S delete mode 100644 isa/rv32ui/divw.S delete mode 100644 isa/rv32ui/lrsc.S delete mode 100644 isa/rv32ui/mul.S delete mode 100644 isa/rv32ui/mulh.S delete mode 100644 isa/rv32ui/mulhsu.S delete mode 100644 isa/rv32ui/mulhu.S delete mode 100644 isa/rv32ui/mulw.S delete mode 100644 isa/rv32ui/rem.S delete mode 100644 isa/rv32ui/remu.S create mode 100644 isa/rv32um/Makefrag create mode 100644 isa/rv32um/div.S create mode 100644 isa/rv32um/divu.S create mode 100644 isa/rv32um/mul.S create mode 100644 isa/rv32um/mulh.S create mode 100644 isa/rv32um/mulhsu.S create mode 100644 isa/rv32um/mulhu.S create mode 100644 isa/rv32um/rem.S create mode 100644 isa/rv32um/remu.S create mode 100644 isa/rv64ua/Makefrag create mode 100644 isa/rv64ua/amoadd_d.S create mode 100644 isa/rv64ua/amoadd_w.S create mode 100644 isa/rv64ua/amoand_d.S create mode 100644 isa/rv64ua/amoand_w.S create mode 100644 isa/rv64ua/amomax_d.S create mode 100644 isa/rv64ua/amomax_w.S create mode 100644 isa/rv64ua/amomaxu_d.S create mode 100644 isa/rv64ua/amomaxu_w.S create mode 100644 isa/rv64ua/amomin_d.S create mode 100644 isa/rv64ua/amomin_w.S create mode 100644 isa/rv64ua/amominu_d.S create mode 100644 isa/rv64ua/amominu_w.S create mode 100644 isa/rv64ua/amoor_d.S create mode 100644 isa/rv64ua/amoor_w.S create mode 100644 isa/rv64ua/amoswap_d.S create mode 100644 isa/rv64ua/amoswap_w.S create mode 100644 isa/rv64ua/amoxor_d.S create mode 100644 isa/rv64ua/amoxor_w.S create mode 100644 isa/rv64ua/lrsc.S delete mode 100644 isa/rv64ui/amoadd_d.S delete mode 100644 isa/rv64ui/amoadd_w.S delete mode 100644 isa/rv64ui/amoand_d.S delete mode 100644 isa/rv64ui/amoand_w.S delete mode 100644 isa/rv64ui/amomax_d.S delete mode 100644 isa/rv64ui/amomax_w.S delete mode 100644 isa/rv64ui/amomaxu_d.S delete mode 100644 isa/rv64ui/amomaxu_w.S delete mode 100644 isa/rv64ui/amomin_d.S delete mode 100644 isa/rv64ui/amomin_w.S delete mode 100644 isa/rv64ui/amominu_d.S delete mode 100644 isa/rv64ui/amominu_w.S delete mode 100644 isa/rv64ui/amoor_d.S delete mode 100644 isa/rv64ui/amoor_w.S delete mode 100644 isa/rv64ui/amoswap_d.S delete mode 100644 isa/rv64ui/amoswap_w.S delete mode 100644 isa/rv64ui/amoxor_d.S delete mode 100644 isa/rv64ui/amoxor_w.S delete mode 100644 isa/rv64ui/div.S delete mode 100644 isa/rv64ui/divu.S delete mode 100644 isa/rv64ui/divuw.S delete mode 100644 isa/rv64ui/divw.S delete mode 100644 isa/rv64ui/lrsc.S delete mode 100644 isa/rv64ui/mul.S delete mode 100644 isa/rv64ui/mulh.S delete mode 100644 isa/rv64ui/mulhsu.S delete mode 100644 isa/rv64ui/mulhu.S delete mode 100644 isa/rv64ui/mulw.S delete mode 100644 isa/rv64ui/rem.S delete mode 100644 isa/rv64ui/remu.S delete mode 100644 isa/rv64ui/remuw.S delete mode 100644 isa/rv64ui/remw.S create mode 100644 isa/rv64um/Makefrag create mode 100644 isa/rv64um/div.S create mode 100644 isa/rv64um/divu.S create mode 100644 isa/rv64um/divuw.S create mode 100644 isa/rv64um/divw.S create mode 100644 isa/rv64um/mul.S create mode 100644 isa/rv64um/mulh.S create mode 100644 isa/rv64um/mulhsu.S create mode 100644 isa/rv64um/mulhu.S create mode 100644 isa/rv64um/mulw.S create mode 100644 isa/rv64um/rem.S create mode 100644 isa/rv64um/remu.S create mode 100644 isa/rv64um/remuw.S create mode 100644 isa/rv64um/remw.S diff --git a/isa/Makefile b/isa/Makefile index d07dfa6..4e1af6c 100644 --- a/isa/Makefile +++ b/isa/Makefile @@ -5,11 +5,15 @@ src_dir := . include $(src_dir)/rv64ui/Makefrag +include $(src_dir)/rv64um/Makefrag +include $(src_dir)/rv64ua/Makefrag include $(src_dir)/rv64uf/Makefrag include $(src_dir)/rv64ud/Makefrag include $(src_dir)/rv64si/Makefrag include $(src_dir)/rv64mi/Makefrag include $(src_dir)/rv32ui/Makefrag +include $(src_dir)/rv32um/Makefrag +include $(src_dir)/rv32ua/Makefrag include $(src_dir)/rv32si/Makefrag include $(src_dir)/rv32mi/Makefrag @@ -62,10 +66,14 @@ tests += $$($(1)_tests) endef $(eval $(call compile_template,rv32ui,-m32)) +$(eval $(call compile_template,rv32um,-m32)) +$(eval $(call compile_template,rv32ua,-m32)) $(eval $(call compile_template,rv32si,-m32)) $(eval $(call compile_template,rv32mi,-m32)) ifeq ($(XLEN),64) $(eval $(call compile_template,rv64ui)) +$(eval $(call compile_template,rv64um)) +$(eval $(call compile_template,rv64ua)) $(eval $(call compile_template,rv64uf)) $(eval $(call compile_template,rv64ud)) $(eval $(call compile_template,rv64si)) diff --git a/isa/rv32ua/Makefrag b/isa/rv32ua/Makefrag new file mode 100644 index 0000000..9af6c7e --- /dev/null +++ b/isa/rv32ua/Makefrag @@ -0,0 +1,12 @@ +#======================================================================= +# Makefrag for rv32ua tests +#----------------------------------------------------------------------- + +rv32ua_sc_tests = \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) +rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) + +spike_tests += $(rv32ua_p_tests) $(rv32ua_v_tests) diff --git a/isa/rv32ua/amoadd_w.S b/isa/rv32ua/amoadd_w.S new file mode 100644 index 0000000..975ae1d --- /dev/null +++ b/isa/rv32ua/amoadd_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoand_w.S b/isa/rv32ua/amoand_w.S new file mode 100644 index 0000000..7c989c2 --- /dev/null +++ b/isa/rv32ua/amoand_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x80000000, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomax_w.S b/isa/rv32ua/amomax_w.S new file mode 100644 index 0000000..698cf26 --- /dev/null +++ b/isa/rv32ua/amomax_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomaxu_w.S b/isa/rv32ua/amomaxu_w.S new file mode 100644 index 0000000..27c4ddf --- /dev/null +++ b/isa/rv32ua/amomaxu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amomin_w.S b/isa/rv32ua/amomin_w.S new file mode 100644 index 0000000..a6a0947 --- /dev/null +++ b/isa/rv32ua/amomin_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amominu_w.S b/isa/rv32ua/amominu_w.S new file mode 100644 index 0000000..ce06e1c --- /dev/null +++ b/isa/rv32ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoor_w.S b/isa/rv32ua/amoor_w.S new file mode 100644 index 0000000..0988c66 --- /dev/null +++ b/isa/rv32ua/amoor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoswap_w.S b/isa/rv32ua/amoswap_w.S new file mode 100644 index 0000000..a32ae74 --- /dev/null +++ b/isa/rv32ua/amoswap_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffff800, \ + li a1, 0x80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/amoxor_w.S b/isa/rv32ua/amoxor_w.S new file mode 100644 index 0000000..d4b775f --- /dev/null +++ b/isa/rv32ua/amoxor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0x80000000, \ + li a0, 0x80000000; \ + li a1, 0xfffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x7ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv32ua/lrsc.S b/isa/rv32ua/lrsc.S new file mode 100644 index 0000000..3a3d05a --- /dev/null +++ b/isa/rv32ua/lrsc.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + add a1, a0, 1024; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +# have each core add its coreid to foo 1000 times +la a0, foo +li a1, 1000 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 1000*ncores*(ncores-1)/2 +TEST_CASE( 4, a2, 0, \ + la a0, foo; \ + li a1, 500; \ + mul a1, a1, a3; \ + add a2, a3, -1; \ + mul a1, a1, a2; \ + lw a2, (a0); \ + sub a2, a2, a1; \ +) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +RVTEST_DATA_END diff --git a/isa/rv32ui/Makefrag b/isa/rv32ui/Makefrag index 4bdebb5..6cb6c08 100644 --- a/isa/rv32ui/Makefrag +++ b/isa/rv32ui/Makefrag @@ -5,19 +5,14 @@ rv32ui_sc_tests = \ simple \ add addi \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ - lrsc \ and andi \ auipc \ beq bge bgeu blt bltu bne \ - div divu \ fence_i \ j jal jalr \ lb lbu lh lhu lw \ lui \ - mul mulh mulhu mulhsu \ or ori \ - rem remu \ sb sh sw \ sll slli \ slt slti \ diff --git a/isa/rv32ui/amoadd_w.S b/isa/rv32ui/amoadd_w.S deleted file mode 100644 index 975ae1d..0000000 --- a/isa/rv32ui/amoadd_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_w.S -#----------------------------------------------------------------------------- -# -# Test amoadd.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x7ffff800, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoand_w.S b/isa/rv32ui/amoand_w.S deleted file mode 100644 index 7c989c2..0000000 --- a/isa/rv32ui/amoand_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand.w.S -#----------------------------------------------------------------------------- -# -# Test amoand.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x80000000, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomax_w.S b/isa/rv32ui/amomax_w.S deleted file mode 100644 index 698cf26..0000000 --- a/isa/rv32ui/amomax_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sw x0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomaxu_w.S b/isa/rv32ui/amomaxu_w.S deleted file mode 100644 index 27c4ddf..0000000 --- a/isa/rv32ui/amomaxu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amomin_w.S b/isa/rv32ui/amomin_w.S deleted file mode 100644 index a6a0947..0000000 --- a/isa/rv32ui/amomin_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amominu_w.S b/isa/rv32ui/amominu_w.S deleted file mode 100644 index ce06e1c..0000000 --- a/isa/rv32ui/amominu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffff; \ - sw x0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoor_w.S b/isa/rv32ui/amoor_w.S deleted file mode 100644 index 0988c66..0000000 --- a/isa/rv32ui/amoor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor.w.S -#----------------------------------------------------------------------------- -# -# Test amoor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoswap_w.S b/isa/rv32ui/amoswap_w.S deleted file mode 100644 index a32ae74..0000000 --- a/isa/rv32ui/amoswap_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffff800, \ - li a1, 0x80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/amoxor_w.S b/isa/rv32ui/amoxor_w.S deleted file mode 100644 index d4b775f..0000000 --- a/isa/rv32ui/amoxor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0x80000000, \ - li a0, 0x80000000; \ - li a1, 0xfffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x7ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x7ffff800, \ - li a1, 0xc0000001; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xbffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv32ui/div.S b/isa/rv32ui/div.S deleted file mode 100644 index a4504a7..0000000 --- a/isa/rv32ui/div.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# div.S -#----------------------------------------------------------------------------- -# -# Test div instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, div, 3, 20, 6 ); - TEST_RR_OP( 3, div, -3, -20, 6 ); - TEST_RR_OP( 4, div, -3, 20, -6 ); - TEST_RR_OP( 5, div, 3, -20, -6 ); - - TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, div, -1, -1<<63, 0 ); - TEST_RR_OP( 9, div, -1, 1, 0 ); - TEST_RR_OP(10, div, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divu.S b/isa/rv32ui/divu.S deleted file mode 100644 index cd348c9..0000000 --- a/isa/rv32ui/divu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divu.S -#----------------------------------------------------------------------------- -# -# Test divu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divu, 3, 20, 6 ); - TEST_RR_OP( 3, divu, 715827879, -20, 6 ); - TEST_RR_OP( 4, divu, 0, 20, -6 ); - TEST_RR_OP( 5, divu, 0, -20, -6 ); - - TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divu, -1, 1, 0 ); - TEST_RR_OP(10, divu, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divuw.S b/isa/rv32ui/divuw.S deleted file mode 100644 index 0868eeb..0000000 --- a/isa/rv32ui/divuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divuw.S -#----------------------------------------------------------------------------- -# -# Test divuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divuw, 3, 20, 6 ); - TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); - TEST_RR_OP( 4, divuw, 0, 20, -6 ); - TEST_RR_OP( 5, divuw, 0, -20, -6 ); - - TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divuw, -1, 1, 0 ); - TEST_RR_OP(10, divuw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/divw.S b/isa/rv32ui/divw.S deleted file mode 100644 index 4d91749..0000000 --- a/isa/rv32ui/divw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divw.S -#----------------------------------------------------------------------------- -# -# Test divw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divw, 3, 20, 6 ); - TEST_RR_OP( 3, divw, -3, -20, 6 ); - TEST_RR_OP( 4, divw, -3, 20, -6 ); - TEST_RR_OP( 5, divw, 3, -20, -6 ); - - TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divw, -1, 1, 0 ); - TEST_RR_OP(10, divw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/lrsc.S b/isa/rv32ui/lrsc.S deleted file mode 100644 index 3a3d05a..0000000 --- a/isa/rv32ui/lrsc.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lrsr.S -#----------------------------------------------------------------------------- -# -# Test LR/SC instructions. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - -# get a unique core id -la a0, coreid -li a1, 1 -amoadd.w a2, a1, (a0) - -# for now, only run this on core 0 -1:li a3, 1 -bgeu a2, a3, 1b - -1: lw a1, (a0) -bltu a1, a3, 1b - -# make sure that sc without a reservation fails. -TEST_CASE( 2, a4, 1, \ - la a0, foo; \ - sc.w a4, x0, (a0); \ -) - -# make sure that sc with the wrong reservation fails. -# TODO is this actually mandatory behavior? -TEST_CASE( 3, a4, 1, \ - la a0, foo; \ - add a1, a0, 1024; \ - lr.w a1, (a1); \ - sc.w a4, a1, (a0); \ -) - -# have each core add its coreid to foo 1000 times -la a0, foo -li a1, 1000 -1: lr.w a4, (a0) -add a4, a4, a2 -sc.w a4, a4, (a0) -bnez a4, 1b -add a1, a1, -1 -bnez a1, 1b - -# wait for all cores to finish -la a0, barrier -li a1, 1 -amoadd.w x0, a1, (a0) -1: lw a1, (a0) -blt a1, a3, 1b -fence - -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ -) - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -barrier: .word 0 -foo: .word 0 -RVTEST_DATA_END diff --git a/isa/rv32ui/mul.S b/isa/rv32ui/mul.S deleted file mode 100644 index 0368629..0000000 --- a/isa/rv32ui/mul.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mul.S -#----------------------------------------------------------------------------- -# -# Test mul instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 ); - TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 ); - - TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff ); - TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mul, 0 ); - TEST_RR_ZERODEST( 29, mul, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulh.S b/isa/rv32ui/mulh.S deleted file mode 100644 index e583f5f..0000000 --- a/isa/rv32ui/mulh.S +++ /dev/null @@ -1,81 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulh.S -#----------------------------------------------------------------------------- -# -# Test mulh instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 ); - - TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulh, 0 ); - TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulhsu.S b/isa/rv32ui/mulhsu.S deleted file mode 100644 index 28b3690..0000000 --- a/isa/rv32ui/mulhsu.S +++ /dev/null @@ -1,83 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhsu.S -#----------------------------------------------------------------------------- -# -# Test mulhsu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); - TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 ); - - - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulhu.S b/isa/rv32ui/mulhu.S deleted file mode 100644 index 601dcff..0000000 --- a/isa/rv32ui/mulhu.S +++ /dev/null @@ -1,82 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhu.S -#----------------------------------------------------------------------------- -# -# Test mulhu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 ); - - TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d ); - TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); - - TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 ); - - TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff ); - TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 ); - TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); - - TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 ); - TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 ); - TEST_RR_ZEROSRC12( 28, mulhu, 0 ); - TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 ); - - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/mulw.S b/isa/rv32ui/mulw.S deleted file mode 100644 index 577c93e..0000000 --- a/isa/rv32ui/mulw.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulw.S -#----------------------------------------------------------------------------- -# -# Test mulw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulw, 0x00000000, 0x00000000, 0xffff8000 ); - TEST_RR_OP( 6, mulw, 0x00000000, 0x80000000, 0x00000000 ); - TEST_RR_OP( 7, mulw, 0x00000000, 0x80000000, 0xffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mulw, 0 ); - TEST_RR_ZERODEST( 29, mulw, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/rem.S b/isa/rv32ui/rem.S deleted file mode 100644 index c318e2c..0000000 --- a/isa/rv32ui/rem.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# rem.S -#----------------------------------------------------------------------------- -# -# Test rem instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, rem, 2, 20, 6 ); - TEST_RR_OP( 3, rem, -2, -20, 6 ); - TEST_RR_OP( 4, rem, 2, 20, -6 ); - TEST_RR_OP( 5, rem, -2, -20, -6 ); - - TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); - TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, rem, 1, 1, 0 ); - TEST_RR_OP(10, rem, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32ui/remu.S b/isa/rv32ui/remu.S deleted file mode 100644 index 38d641d..0000000 --- a/isa/rv32ui/remu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remu.S -#----------------------------------------------------------------------------- -# -# Test remu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV32U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remu, 2, 20, 6 ); - TEST_RR_OP( 3, remu, 2, -20, 6 ); - TEST_RR_OP( 4, remu, 20, 20, -6 ); - TEST_RR_OP( 5, remu, -20, -20, -6 ); - - TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); - TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, remu, 1, 1, 0 ); - TEST_RR_OP(10, remu, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv32um/Makefrag b/isa/rv32um/Makefrag new file mode 100644 index 0000000..50bffc8 --- /dev/null +++ b/isa/rv32um/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv32um tests +#----------------------------------------------------------------------- + +rv32um_sc_tests = \ + div divu \ + mul mulh mulhsu mulhu \ + rem remu \ + +rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) +rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests)) + +spike_tests += $(rv32um_p_tests) $(rv32um_v_tests) diff --git a/isa/rv32um/div.S b/isa/rv32um/div.S new file mode 100644 index 0000000..a4504a7 --- /dev/null +++ b/isa/rv32um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/divu.S b/isa/rv32um/divu.S new file mode 100644 index 0000000..cd348c9 --- /dev/null +++ b/isa/rv32um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 715827879, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mul.S b/isa/rv32um/mul.S new file mode 100644 index 0000000..0368629 --- /dev/null +++ b/isa/rv32um/mul.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x00001200, 0x00007e00, 0xb6db6db7 ); + TEST_RR_OP(33, mul, 0x00001240, 0x00007fc0, 0xb6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mul, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x00000000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mul, 0x0000ff7f, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mul, 0x0000ff7f, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(34, mul, 0x00000000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(35, mul, 0x00000001, 0xffffffff, 0xffffffff ); + TEST_RR_OP(36, mul, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(37, mul, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulh.S b/isa/rv32um/mulh.S new file mode 100644 index 0000000..e583f5f --- /dev/null +++ b/isa/rv32um/mulh.S @@ -0,0 +1,81 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulh, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x00000000, 0x80000000, 0x00000000 ); + + TEST_RR_OP(30, mulh, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulh, 0xffff0081, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulh, 0x00010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulh, 0x00000000, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulh, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulh, 0xffffffff, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<20, 34<<20 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulhsu.S b/isa/rv32um/mulhsu.S new file mode 100644 index 0000000..28b3690 --- /dev/null +++ b/isa/rv32um/mulhsu.S @@ -0,0 +1,83 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0x80004000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhsu, 0xffff0081, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhsu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhsu, 0xff010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhsu, 0xffffffff, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhsu, 0xffffffff, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhsu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<20, 34<<20 ); + + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/mulhu.S b/isa/rv32um/mulhu.S new file mode 100644 index 0000000..601dcff --- /dev/null +++ b/isa/rv32um/mulhu.S @@ -0,0 +1,82 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x00000000, 0x00000000, 0xffff8000 ); + TEST_RR_OP( 6, mulhu, 0x00000000, 0x80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0x7fffc000, 0x80000000, 0xffff8000 ); + + TEST_RR_OP(30, mulhu, 0x0001fefe, 0xaaaaaaab, 0x0002fe7d ); + TEST_RR_OP(31, mulhu, 0x0001fefe, 0x0002fe7d, 0xaaaaaaab ); + + TEST_RR_OP(32, mulhu, 0xfe010000, 0xff000000, 0xff000000 ); + + TEST_RR_OP(33, mulhu, 0xfffffffe, 0xffffffff, 0xffffffff ); + TEST_RR_OP(34, mulhu, 0x00000000, 0xffffffff, 0x00000001 ); + TEST_RR_OP(35, mulhu, 0x00000000, 0x00000001, 0xffffffff ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 43264, 13<<20 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 42240, 15<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 36608, 13<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 39424, 14<<20, 11<<20 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 42240, 15<<20, 11<<20 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<26 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<26 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<20, 34<<20 ); + + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/rem.S b/isa/rv32um/rem.S new file mode 100644 index 0000000..c318e2c --- /dev/null +++ b/isa/rv32um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv32um/remu.S b/isa/rv32um/remu.S new file mode 100644 index 0000000..38d641d --- /dev/null +++ b/isa/rv32um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV32U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64ua/Makefrag b/isa/rv64ua/Makefrag new file mode 100644 index 0000000..3af8856 --- /dev/null +++ b/isa/rv64ua/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64ua tests +#----------------------------------------------------------------------- + +rv64ua_sc_tests = \ + amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ + amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ + lrsc \ + +rv64ua_p_tests = $(addprefix rv64ua-p-, $(rv64ua_sc_tests)) +rv64ua_v_tests = $(addprefix rv64ua-v-, $(rv64ua_sc_tests)) + +spike_tests += $(rv64ua_p_tests) $(rv64ua_v_tests) diff --git a/isa/rv64ua/amoadd_d.S b/isa/rv64ua/amoadd_d.S new file mode 100644 index 0000000..c356bed --- /dev/null +++ b/isa/rv64ua/amoadd_d.S @@ -0,0 +1,64 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_d.S +#----------------------------------------------------------------------------- +# +# Test amoadd.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff7ffff800, \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoadd.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoadd_w.S b/isa/rv64ua/amoadd_w.S new file mode 100644 index 0000000..b3d1953 --- /dev/null +++ b/isa/rv64ua/amoadd_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoadd_w.S +#----------------------------------------------------------------------------- +# +# Test amoadd.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xffffffff80000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoadd.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_d.S b/isa/rv64ua/amoand_d.S new file mode 100644 index 0000000..13019ae --- /dev/null +++ b/isa/rv64ua/amoand_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand_d.S +#----------------------------------------------------------------------------- +# +# Test amoand.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoand.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoand_w.S b/isa/rv64ua/amoand_w.S new file mode 100644 index 0000000..a843888 --- /dev/null +++ b/isa/rv64ua/amoand_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoand.w.S +#----------------------------------------------------------------------------- +# +# Test amoand.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xffffffff80000000, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoand.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_d.S b/isa/rv64ua/amomax_d.S new file mode 100644 index 0000000..ea7e2d3 --- /dev/null +++ b/isa/rv64ua/amomax_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sd x0, 0(a3); \ + amomax.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomax_w.S b/isa/rv64ua/amomax_w.S new file mode 100644 index 0000000..b3adbf0 --- /dev/null +++ b/isa/rv64ua/amomax_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomax_d.S +#----------------------------------------------------------------------------- +# +# Test amomax.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 1; \ + sw x0, 0(a3); \ + amomax.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 1, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_d.S b/isa/rv64ua/amomaxu_d.S new file mode 100644 index 0000000..b340873 --- /dev/null +++ b/isa/rv64ua/amomaxu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomaxu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomaxu_w.S b/isa/rv64ua/amomaxu_w.S new file mode 100644 index 0000000..41346d1 --- /dev/null +++ b/isa/rv64ua/amomaxu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomaxu_d.S +#----------------------------------------------------------------------------- +# +# Test amomaxu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomaxu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_d.S b/isa/rv64ua/amomin_d.S new file mode 100644 index 0000000..e6febbb --- /dev/null +++ b/isa/rv64ua/amomin_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amomin.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amomin_w.S b/isa/rv64ua/amomin_w.S new file mode 100644 index 0000000..96b547b --- /dev/null +++ b/isa/rv64ua/amomin_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amomin_d.S +#----------------------------------------------------------------------------- +# +# Test amomin.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amomin.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_d.S b/isa/rv64ua/amominu_d.S new file mode 100644 index 0000000..a1013f3 --- /dev/null +++ b/isa/rv64ua/amominu_d.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sd x0, 0(a3); \ + amominu.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amominu_w.S b/isa/rv64ua/amominu_w.S new file mode 100644 index 0000000..0a9e265 --- /dev/null +++ b/isa/rv64ua/amominu_w.S @@ -0,0 +1,49 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amominu_d.S +#----------------------------------------------------------------------------- +# +# Test amominu.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_CASE(4, a4, 0, \ + li a1, 0xffffffffffffffff; \ + sw x0, 0(a3); \ + amominu.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_d.S b/isa/rv64ua/amoor_d.S new file mode 100644 index 0000000..507e877 --- /dev/null +++ b/isa/rv64ua/amoor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor_d.S +#----------------------------------------------------------------------------- +# +# Test amoor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoor_w.S b/isa/rv64ua/amoor_w.S new file mode 100644 index 0000000..47978ba --- /dev/null +++ b/isa/rv64ua/amoor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoor.w.S +#----------------------------------------------------------------------------- +# +# Test amoor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_d.S b/isa/rv64ua/amoswap_d.S new file mode 100644 index 0000000..628f537 --- /dev/null +++ b/isa/rv64ua/amoswap_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap.d.S +#----------------------------------------------------------------------------- +# +# Test amoswap.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoswap.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoswap_w.S b/isa/rv64ua/amoswap_w.S new file mode 100644 index 0000000..c09b866 --- /dev/null +++ b/isa/rv64ua/amoswap_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoswap_w.S +#----------------------------------------------------------------------------- +# +# Test amoswap.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sw a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0xfffffffffffff800, \ + li a1, 0x0000000080000000; \ + li a4, 16384; \ + add a5, a3, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + add a5, a5, a4; \ + lw x0, 0(a5); \ + amoswap.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_d.S b/isa/rv64ua/amoxor_d.S new file mode 100644 index 0000000..f446121 --- /dev/null +++ b/isa/rv64ua/amoxor_d.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_d.S +#----------------------------------------------------------------------------- +# +# Test amoxor.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 1; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.d a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/amoxor_w.S b/isa/rv64ua/amoxor_w.S new file mode 100644 index 0000000..2b92323 --- /dev/null +++ b/isa/rv64ua/amoxor_w.S @@ -0,0 +1,65 @@ +# See LICENSE for license details. + +#***************************************************************************** +# amoxor_w.S +#----------------------------------------------------------------------------- +# +# Test amoxor.w instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + TEST_CASE(2, a4, 0xffffffff80000000, \ + li a0, 0xffffffff80000000; \ + li a1, 0xfffffffffffff800; \ + la a3, amo_operand; \ + sd a0, 0(a3); \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + nop; nop; nop; nop; \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) + + # try again after a cache miss + TEST_CASE(4, a4, 0x000000007ffff800, \ + li a1, 0xc0000001; \ + li a4, 16384; \ + add a5, a3, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + add a5, a5, a4; \ + ld x0, 0(a5); \ + amoxor.w a4, a1, 0(a3); \ + ) + + TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END + + .bss + .align 3 +amo_operand: + .dword 0 + .skip 65536 diff --git a/isa/rv64ua/lrsc.S b/isa/rv64ua/lrsc.S new file mode 100644 index 0000000..9422739 --- /dev/null +++ b/isa/rv64ua/lrsc.S @@ -0,0 +1,84 @@ +# See LICENSE for license details. + +#***************************************************************************** +# lrsr.S +#----------------------------------------------------------------------------- +# +# Test LR/SC instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + +# get a unique core id +la a0, coreid +li a1, 1 +amoadd.w a2, a1, (a0) + +# for now, only run this on core 0 +1:li a3, 1 +bgeu a2, a3, 1b + +1: lw a1, (a0) +bltu a1, a3, 1b + +# make sure that sc without a reservation fails. +TEST_CASE( 2, a4, 1, \ + la a0, foo; \ + sc.w a4, x0, (a0); \ +) + +# make sure that sc with the wrong reservation fails. +# TODO is this actually mandatory behavior? +TEST_CASE( 3, a4, 1, \ + la a0, foo; \ + add a1, a0, 1024; \ + lr.w a1, (a1); \ + sc.w a4, a1, (a0); \ +) + +# have each core add its coreid to foo 1000 times +la a0, foo +li a1, 1000 +1: lr.w a4, (a0) +add a4, a4, a2 +sc.w a4, a4, (a0) +bnez a4, 1b +add a1, a1, -1 +bnez a1, 1b + +# wait for all cores to finish +la a0, barrier +li a1, 1 +amoadd.w x0, a1, (a0) +1: lw a1, (a0) +blt a1, a3, 1b +fence + +# expected result is 1000*ncores*(ncores-1)/2 +TEST_CASE( 4, a2, 0, \ + la a0, foo; \ + li a1, 500; \ + mul a1, a1, a3; \ + add a2, a3, -1; \ + mul a1, a1, a2; \ + lw a2, (a0); \ + sub a2, a2, a1; \ +) + +TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +coreid: .word 0 +barrier: .word 0 +foo: .word 0 +RVTEST_DATA_END diff --git a/isa/rv64ui/Makefrag b/isa/rv64ui/Makefrag index 4af2504..7920b99 100644 --- a/isa/rv64ui/Makefrag +++ b/isa/rv64ui/Makefrag @@ -4,21 +4,15 @@ rv64ui_sc_tests = \ add addi addiw addw \ - amoadd_d amoand_d amomax_d amomaxu_d amomin_d amominu_d amoor_d amoxor_d amoswap_d \ - amoadd_w amoand_w amomax_w amomaxu_w amomin_w amominu_w amoor_w amoxor_w amoswap_w \ - lrsc \ and andi \ auipc \ beq bge bgeu blt bltu bne \ - div divu divuw divw \ example simple \ fence_i \ j jal jalr \ lb lbu lh lhu lw lwu ld \ lui \ - mul mulh mulhsu mulhu mulw \ or ori \ - rem remu remuw remw \ sb sh sw sd \ sll slli slliw sllw \ slt slti sltiu sltu \ diff --git a/isa/rv64ui/amoadd_d.S b/isa/rv64ui/amoadd_d.S deleted file mode 100644 index c356bed..0000000 --- a/isa/rv64ui/amoadd_d.S +++ /dev/null @@ -1,64 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_d.S -#----------------------------------------------------------------------------- -# -# Test amoadd.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff7ffff800, \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoadd.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff7ffff000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoadd_w.S b/isa/rv64ui/amoadd_w.S deleted file mode 100644 index b3d1953..0000000 --- a/isa/rv64ui/amoadd_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoadd_w.S -#----------------------------------------------------------------------------- -# -# Test amoadd.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x000000007ffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 0xffffffff80000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoadd.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoand_d.S b/isa/rv64ui/amoand_d.S deleted file mode 100644 index 13019ae..0000000 --- a/isa/rv64ui/amoand_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand_d.S -#----------------------------------------------------------------------------- -# -# Test amoand.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff80000000, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoand.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoand_w.S b/isa/rv64ui/amoand_w.S deleted file mode 100644 index a843888..0000000 --- a/isa/rv64ui/amoand_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoand.w.S -#----------------------------------------------------------------------------- -# -# Test amoand.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xffffffff80000000, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoand.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomax_d.S b/isa/rv64ui/amomax_d.S deleted file mode 100644 index ea7e2d3..0000000 --- a/isa/rv64ui/amomax_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomax.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sd x0, 0(a3); \ - amomax.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomax_w.S b/isa/rv64ui/amomax_w.S deleted file mode 100644 index b3adbf0..0000000 --- a/isa/rv64ui/amomax_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomax_d.S -#----------------------------------------------------------------------------- -# -# Test amomax.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 1; \ - sw x0, 0(a3); \ - amomax.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 1, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomaxu_d.S b/isa/rv64ui/amomaxu_d.S deleted file mode 100644 index b340873..0000000 --- a/isa/rv64ui/amomaxu_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomaxu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amomaxu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomaxu_w.S b/isa/rv64ui/amomaxu_w.S deleted file mode 100644 index 41346d1..0000000 --- a/isa/rv64ui/amomaxu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomaxu_d.S -#----------------------------------------------------------------------------- -# -# Test amomaxu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amomaxu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomin_d.S b/isa/rv64ui/amomin_d.S deleted file mode 100644 index e6febbb..0000000 --- a/isa/rv64ui/amomin_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amomin.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amomin.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amomin_w.S b/isa/rv64ui/amomin_w.S deleted file mode 100644 index 96b547b..0000000 --- a/isa/rv64ui/amomin_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amomin_d.S -#----------------------------------------------------------------------------- -# -# Test amomin.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amomin.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffffffffff, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amominu_d.S b/isa/rv64ui/amominu_d.S deleted file mode 100644 index a1013f3..0000000 --- a/isa/rv64ui/amominu_d.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - amominu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, ld a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sd x0, 0(a3); \ - amominu.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amominu_w.S b/isa/rv64ui/amominu_w.S deleted file mode 100644 index 0a9e265..0000000 --- a/isa/rv64ui/amominu_w.S +++ /dev/null @@ -1,49 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amominu_d.S -#----------------------------------------------------------------------------- -# -# Test amominu.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_CASE(4, a4, 0, \ - li a1, 0xffffffffffffffff; \ - sw x0, 0(a3); \ - amominu.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoor_d.S b/isa/rv64ui/amoor_d.S deleted file mode 100644 index 507e877..0000000 --- a/isa/rv64ui/amoor_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor_d.S -#----------------------------------------------------------------------------- -# -# Test amoor.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoor_w.S b/isa/rv64ui/amoor_w.S deleted file mode 100644 index 47978ba..0000000 --- a/isa/rv64ui/amoor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoor.w.S -#----------------------------------------------------------------------------- -# -# Test amoor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xfffffffffffff801, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoswap_d.S b/isa/rv64ui/amoswap_d.S deleted file mode 100644 index 628f537..0000000 --- a/isa/rv64ui/amoswap_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap.d.S -#----------------------------------------------------------------------------- -# -# Test amoswap.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoswap.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x0000000080000000, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoswap_w.S b/isa/rv64ui/amoswap_w.S deleted file mode 100644 index c09b866..0000000 --- a/isa/rv64ui/amoswap_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoswap_w.S -#----------------------------------------------------------------------------- -# -# Test amoswap.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sw a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xfffffffffffff800, lw a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0xfffffffffffff800, \ - li a1, 0x0000000080000000; \ - li a4, 16384; \ - add a5, a3, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - add a5, a5, a4; \ - lw x0, 0(a5); \ - amoswap.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffff80000000, lw a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoxor_d.S b/isa/rv64ui/amoxor_d.S deleted file mode 100644 index f446121..0000000 --- a/isa/rv64ui/amoxor_d.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_d.S -#----------------------------------------------------------------------------- -# -# Test amoxor.d instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0x000000007ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 1; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoxor.d a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0x000000007ffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/amoxor_w.S b/isa/rv64ui/amoxor_w.S deleted file mode 100644 index 2b92323..0000000 --- a/isa/rv64ui/amoxor_w.S +++ /dev/null @@ -1,65 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# amoxor_w.S -#----------------------------------------------------------------------------- -# -# Test amoxor.w instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - TEST_CASE(2, a4, 0xffffffff80000000, \ - li a0, 0xffffffff80000000; \ - li a1, 0xfffffffffffff800; \ - la a3, amo_operand; \ - sd a0, 0(a3); \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - nop; nop; nop; nop; \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(3, a5, 0xffffffff7ffff800, ld a5, 0(a3)) - - # try again after a cache miss - TEST_CASE(4, a4, 0x000000007ffff800, \ - li a1, 0xc0000001; \ - li a4, 16384; \ - add a5, a3, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - add a5, a5, a4; \ - ld x0, 0(a5); \ - amoxor.w a4, a1, 0(a3); \ - ) - - TEST_CASE(5, a5, 0xffffffffbffff801, ld a5, 0(a3)) - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END - - .bss - .align 3 -amo_operand: - .dword 0 - .skip 65536 diff --git a/isa/rv64ui/div.S b/isa/rv64ui/div.S deleted file mode 100644 index ee21f0c..0000000 --- a/isa/rv64ui/div.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# div.S -#----------------------------------------------------------------------------- -# -# Test div instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, div, 3, 20, 6 ); - TEST_RR_OP( 3, div, -3, -20, 6 ); - TEST_RR_OP( 4, div, -3, 20, -6 ); - TEST_RR_OP( 5, div, 3, -20, -6 ); - - TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, div, -1, -1<<63, 0 ); - TEST_RR_OP( 9, div, -1, 1, 0 ); - TEST_RR_OP(10, div, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divu.S b/isa/rv64ui/divu.S deleted file mode 100644 index e63fd65..0000000 --- a/isa/rv64ui/divu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divu.S -#----------------------------------------------------------------------------- -# -# Test divu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divu, 3, 20, 6 ); - TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); - TEST_RR_OP( 4, divu, 0, 20, -6 ); - TEST_RR_OP( 5, divu, 0, -20, -6 ); - - TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); - TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); - TEST_RR_OP( 9, divu, -1, 1, 0 ); - TEST_RR_OP(10, divu, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divuw.S b/isa/rv64ui/divuw.S deleted file mode 100644 index 4c9eee7..0000000 --- a/isa/rv64ui/divuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divuw.S -#----------------------------------------------------------------------------- -# -# Test divuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divuw, 3, 20, 6 ); - TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); - TEST_RR_OP( 4, divuw, 0, 20, -6 ); - TEST_RR_OP( 5, divuw, 0, -20, -6 ); - - TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divuw, -1, 1, 0 ); - TEST_RR_OP(10, divuw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/divw.S b/isa/rv64ui/divw.S deleted file mode 100644 index 4cffa1a..0000000 --- a/isa/rv64ui/divw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# divw.S -#----------------------------------------------------------------------------- -# -# Test divw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, divw, 3, 20, 6 ); - TEST_RR_OP( 3, divw, -3, -20, 6 ); - TEST_RR_OP( 4, divw, -3, 20, -6 ); - TEST_RR_OP( 5, divw, 3, -20, -6 ); - - TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); - TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); - TEST_RR_OP( 9, divw, -1, 1, 0 ); - TEST_RR_OP(10, divw, -1, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/lrsc.S b/isa/rv64ui/lrsc.S deleted file mode 100644 index 9422739..0000000 --- a/isa/rv64ui/lrsc.S +++ /dev/null @@ -1,84 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# lrsr.S -#----------------------------------------------------------------------------- -# -# Test LR/SC instructions. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - -# get a unique core id -la a0, coreid -li a1, 1 -amoadd.w a2, a1, (a0) - -# for now, only run this on core 0 -1:li a3, 1 -bgeu a2, a3, 1b - -1: lw a1, (a0) -bltu a1, a3, 1b - -# make sure that sc without a reservation fails. -TEST_CASE( 2, a4, 1, \ - la a0, foo; \ - sc.w a4, x0, (a0); \ -) - -# make sure that sc with the wrong reservation fails. -# TODO is this actually mandatory behavior? -TEST_CASE( 3, a4, 1, \ - la a0, foo; \ - add a1, a0, 1024; \ - lr.w a1, (a1); \ - sc.w a4, a1, (a0); \ -) - -# have each core add its coreid to foo 1000 times -la a0, foo -li a1, 1000 -1: lr.w a4, (a0) -add a4, a4, a2 -sc.w a4, a4, (a0) -bnez a4, 1b -add a1, a1, -1 -bnez a1, 1b - -# wait for all cores to finish -la a0, barrier -li a1, 1 -amoadd.w x0, a1, (a0) -1: lw a1, (a0) -blt a1, a3, 1b -fence - -# expected result is 1000*ncores*(ncores-1)/2 -TEST_CASE( 4, a2, 0, \ - la a0, foo; \ - li a1, 500; \ - mul a1, a1, a3; \ - add a2, a3, -1; \ - mul a1, a1, a2; \ - lw a2, (a0); \ - sub a2, a2, a1; \ -) - -TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -coreid: .word 0 -barrier: .word 0 -foo: .word 0 -RVTEST_DATA_END diff --git a/isa/rv64ui/mul.S b/isa/rv64ui/mul.S deleted file mode 100644 index c647e97..0000000 --- a/isa/rv64ui/mul.S +++ /dev/null @@ -1,78 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mul.S -#----------------------------------------------------------------------------- -# -# Test mul instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); - TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); - - TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); - TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mul, 0 ); - TEST_RR_ZERODEST( 29, mul, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulh.S b/isa/rv64ui/mulh.S deleted file mode 100644 index 1fd12a1..0000000 --- a/isa/rv64ui/mulh.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulh.S -#----------------------------------------------------------------------------- -# -# Test mulh instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulh, 0 ); - TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulhsu.S b/isa/rv64ui/mulhsu.S deleted file mode 100644 index c037db2..0000000 --- a/isa/rv64ui/mulhsu.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhsu.S -#----------------------------------------------------------------------------- -# -# Test mulhsu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); - TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulhu.S b/isa/rv64ui/mulhu.S deleted file mode 100644 index aa7b762..0000000 --- a/isa/rv64ui/mulhu.S +++ /dev/null @@ -1,75 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulhu.S -#----------------------------------------------------------------------------- -# -# Test mulhu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); - - TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); - TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 ); - - TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 ); - TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 ); - TEST_RR_ZEROSRC12( 28, mulhu, 0 ); - TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/mulw.S b/isa/rv64ui/mulw.S deleted file mode 100644 index 379c3f2..0000000 --- a/isa/rv64ui/mulw.S +++ /dev/null @@ -1,72 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# mulw.S -#----------------------------------------------------------------------------- -# -# Test mulw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); - TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); - TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); - - TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); - TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); - TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); - - #------------------------------------------------------------- - # Source/Destination tests - #------------------------------------------------------------- - - TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); - TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); - TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); - - #------------------------------------------------------------- - # Bypassing tests - #------------------------------------------------------------- - - TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); - TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); - TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); - - TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); - TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); - TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); - TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); - - TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); - TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); - TEST_RR_ZEROSRC12( 28, mulw, 0 ); - TEST_RR_ZERODEST( 29, mulw, 33, 34 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/rem.S b/isa/rv64ui/rem.S deleted file mode 100644 index e3248ff..0000000 --- a/isa/rv64ui/rem.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# rem.S -#----------------------------------------------------------------------------- -# -# Test rem instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, rem, 2, 20, 6 ); - TEST_RR_OP( 3, rem, -2, -20, 6 ); - TEST_RR_OP( 4, rem, 2, 20, -6 ); - TEST_RR_OP( 5, rem, -2, -20, -6 ); - - TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); - TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); - - TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, rem, 1, 1, 0 ); - TEST_RR_OP(10, rem, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remu.S b/isa/rv64ui/remu.S deleted file mode 100644 index 6946d0d..0000000 --- a/isa/rv64ui/remu.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remu.S -#----------------------------------------------------------------------------- -# -# Test remu instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remu, 2, 20, 6 ); - TEST_RR_OP( 3, remu, 2, -20, 6 ); - TEST_RR_OP( 4, remu, 20, 20, -6 ); - TEST_RR_OP( 5, remu, -20, -20, -6 ); - - TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); - TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); - - TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); - TEST_RR_OP( 9, remu, 1, 1, 0 ); - TEST_RR_OP(10, remu, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remuw.S b/isa/rv64ui/remuw.S deleted file mode 100644 index 334b5c5..0000000 --- a/isa/rv64ui/remuw.S +++ /dev/null @@ -1,41 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remuw.S -#----------------------------------------------------------------------------- -# -# Test remuw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remuw, 2, 20, 6 ); - TEST_RR_OP( 3, remuw, 2, -20, 6 ); - TEST_RR_OP( 4, remuw, 20, 20, -6 ); - TEST_RR_OP( 5, remuw, -20, -20, -6 ); - - TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); - TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); - - TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); - TEST_RR_OP( 9, remuw, 1, 1, 0 ); - TEST_RR_OP(10, remuw, 0, 0, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64ui/remw.S b/isa/rv64ui/remw.S deleted file mode 100644 index 3ae8e3d..0000000 --- a/isa/rv64ui/remw.S +++ /dev/null @@ -1,42 +0,0 @@ -# See LICENSE for license details. - -#***************************************************************************** -# remw.S -#----------------------------------------------------------------------------- -# -# Test remw instruction. -# - -#include "riscv_test.h" -#include "test_macros.h" - -RVTEST_RV64U -RVTEST_CODE_BEGIN - - #------------------------------------------------------------- - # Arithmetic tests - #------------------------------------------------------------- - - TEST_RR_OP( 2, remw, 2, 20, 6 ); - TEST_RR_OP( 3, remw, -2, -20, 6 ); - TEST_RR_OP( 4, remw, 2, 20, -6 ); - TEST_RR_OP( 5, remw, -2, -20, -6 ); - - TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); - TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); - - TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); - TEST_RR_OP( 9, remw, 1, 1, 0 ); - TEST_RR_OP(10, remw, 0, 0, 0 ); - TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); - - TEST_PASSFAIL - -RVTEST_CODE_END - - .data -RVTEST_DATA_BEGIN - - TEST_DATA - -RVTEST_DATA_END diff --git a/isa/rv64um/Makefrag b/isa/rv64um/Makefrag new file mode 100644 index 0000000..360bd7a --- /dev/null +++ b/isa/rv64um/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64um tests +#----------------------------------------------------------------------- + +rv64um_sc_tests = \ + div divu divuw divw \ + mul mulh mulhsu mulhu mulw \ + rem remu remuw remw \ + +rv64um_p_tests = $(addprefix rv64um-p-, $(rv64um_sc_tests)) +rv64um_v_tests = $(addprefix rv64um-v-, $(rv64um_sc_tests)) + +spike_tests += $(rv64um_p_tests) $(rv64um_v_tests) diff --git a/isa/rv64um/div.S b/isa/rv64um/div.S new file mode 100644 index 0000000..ee21f0c --- /dev/null +++ b/isa/rv64um/div.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# div.S +#----------------------------------------------------------------------------- +# +# Test div instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, div, 3, 20, 6 ); + TEST_RR_OP( 3, div, -3, -20, 6 ); + TEST_RR_OP( 4, div, -3, 20, -6 ); + TEST_RR_OP( 5, div, 3, -20, -6 ); + + TEST_RR_OP( 6, div, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, div, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, div, -1, -1<<63, 0 ); + TEST_RR_OP( 9, div, -1, 1, 0 ); + TEST_RR_OP(10, div, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divu.S b/isa/rv64um/divu.S new file mode 100644 index 0000000..e63fd65 --- /dev/null +++ b/isa/rv64um/divu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divu.S +#----------------------------------------------------------------------------- +# +# Test divu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divu, 3, 20, 6 ); + TEST_RR_OP( 3, divu, 3074457345618258599, -20, 6 ); + TEST_RR_OP( 4, divu, 0, 20, -6 ); + TEST_RR_OP( 5, divu, 0, -20, -6 ); + + TEST_RR_OP( 6, divu, -1<<63, -1<<63, 1 ); + TEST_RR_OP( 7, divu, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, divu, -1, -1<<63, 0 ); + TEST_RR_OP( 9, divu, -1, 1, 0 ); + TEST_RR_OP(10, divu, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divuw.S b/isa/rv64um/divuw.S new file mode 100644 index 0000000..4c9eee7 --- /dev/null +++ b/isa/rv64um/divuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divuw.S +#----------------------------------------------------------------------------- +# +# Test divuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divuw, 3, 20, 6 ); + TEST_RR_OP( 3, divuw, 715827879, -20 << 32 >> 32, 6 ); + TEST_RR_OP( 4, divuw, 0, 20, -6 ); + TEST_RR_OP( 5, divuw, 0, -20, -6 ); + + TEST_RR_OP( 6, divuw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divuw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, divuw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divuw, -1, 1, 0 ); + TEST_RR_OP(10, divuw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/divw.S b/isa/rv64um/divw.S new file mode 100644 index 0000000..4cffa1a --- /dev/null +++ b/isa/rv64um/divw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# divw.S +#----------------------------------------------------------------------------- +# +# Test divw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, divw, 3, 20, 6 ); + TEST_RR_OP( 3, divw, -3, -20, 6 ); + TEST_RR_OP( 4, divw, -3, 20, -6 ); + TEST_RR_OP( 5, divw, 3, -20, -6 ); + + TEST_RR_OP( 6, divw, -1<<31, -1<<31, 1 ); + TEST_RR_OP( 7, divw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, divw, -1, -1<<31, 0 ); + TEST_RR_OP( 9, divw, -1, 1, 0 ); + TEST_RR_OP(10, divw, -1, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mul.S b/isa/rv64um/mul.S new file mode 100644 index 0000000..c647e97 --- /dev/null +++ b/isa/rv64um/mul.S @@ -0,0 +1,78 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mul.S +#----------------------------------------------------------------------------- +# +# Test mul instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP(32, mul, 0x0000000000001200, 0x0000000000007e00, 0x6db6db6db6db6db7 ); + TEST_RR_OP(33, mul, 0x0000000000001240, 0x0000000000007fc0, 0x6db6db6db6db6db7 ); + + TEST_RR_OP( 2, mul, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mul, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mul, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mul, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mul, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mul, 0x0000400000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mul, 0x000000000000ff7f, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mul, 0x000000000000ff7f, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mul, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mul, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mul, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mul, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mul, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mul, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mul, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mul, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mul, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mul, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mul, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mul, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mul, 0 ); + TEST_RR_ZERODEST( 29, mul, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulh.S b/isa/rv64um/mulh.S new file mode 100644 index 0000000..1fd12a1 --- /dev/null +++ b/isa/rv64um/mulh.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulh.S +#----------------------------------------------------------------------------- +# +# Test mulh instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulh, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulh, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulh, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulh, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulh, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulh, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulh, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulh, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulh, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulh, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulh, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulh, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulh, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulh, 0 ); + TEST_RR_ZERODEST( 29, mulh, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulhsu.S b/isa/rv64um/mulhsu.S new file mode 100644 index 0000000..c037db2 --- /dev/null +++ b/isa/rv64um/mulhsu.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhsu.S +#----------------------------------------------------------------------------- +# +# Test mulhsu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhsu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhsu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhsu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhsu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhsu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhsu, 0xffffffff80000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhsu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhsu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhsu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhsu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhsu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhsu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhsu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhsu, 0 ); + TEST_RR_ZERODEST( 29, mulhsu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulhu.S b/isa/rv64um/mulhu.S new file mode 100644 index 0000000..aa7b762 --- /dev/null +++ b/isa/rv64um/mulhu.S @@ -0,0 +1,75 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulhu.S +#----------------------------------------------------------------------------- +# +# Test mulhu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulhu, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulhu, 0x00000000, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulhu, 0x00000000, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulhu, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulhu, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulhu, 0xffffffff7fff8000, 0xffffffff80000000, 0xffffffffffff8000 ); + + TEST_RR_OP(30, mulhu, 0x000000000001fefe, 0xaaaaaaaaaaaaaaab, 0x000000000002fe7d ); + TEST_RR_OP(31, mulhu, 0x000000000001fefe, 0x000000000002fe7d, 0xaaaaaaaaaaaaaaab ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC2_EQ_DEST( 9, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_EQ_DEST( 10, mulhu, 169, 13<<32 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 12, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_DEST_BYPASS( 13, 2, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulhu, 165, 15<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulhu, 143, 13<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulhu, 154, 14<<32, 11<<32 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulhu, 165, 15<<32, 11<<32 ); + + TEST_RR_ZEROSRC1( 26, mulhu, 0, 31<<32 ); + TEST_RR_ZEROSRC2( 27, mulhu, 0, 32<<32 ); + TEST_RR_ZEROSRC12( 28, mulhu, 0 ); + TEST_RR_ZERODEST( 29, mulhu, 33<<32, 34<<32 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/mulw.S b/isa/rv64um/mulw.S new file mode 100644 index 0000000..379c3f2 --- /dev/null +++ b/isa/rv64um/mulw.S @@ -0,0 +1,72 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mulw.S +#----------------------------------------------------------------------------- +# +# Test mulw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, mulw, 0x00000000, 0x00000000, 0x00000000 ); + TEST_RR_OP( 3, mulw, 0x00000001, 0x00000001, 0x00000001 ); + TEST_RR_OP( 4, mulw, 0x00000015, 0x00000003, 0x00000007 ); + + TEST_RR_OP( 5, mulw, 0x0000000000000000, 0x0000000000000000, 0xffffffffffff8000 ); + TEST_RR_OP( 6, mulw, 0x0000000000000000, 0xffffffff80000000, 0x00000000 ); + TEST_RR_OP( 7, mulw, 0x0000000000000000, 0xffffffff80000000, 0xffffffffffff8000 ); + + #------------------------------------------------------------- + # Source/Destination tests + #------------------------------------------------------------- + + TEST_RR_SRC1_EQ_DEST( 8, mulw, 143, 13, 11 ); + TEST_RR_SRC2_EQ_DEST( 9, mulw, 154, 14, 11 ); + TEST_RR_SRC12_EQ_DEST( 10, mulw, 169, 13 ); + + #------------------------------------------------------------- + # Bypassing tests + #------------------------------------------------------------- + + TEST_RR_DEST_BYPASS( 11, 0, mulw, 143, 13, 11 ); + TEST_RR_DEST_BYPASS( 12, 1, mulw, 154, 14, 11 ); + TEST_RR_DEST_BYPASS( 13, 2, mulw, 165, 15, 11 ); + + TEST_RR_SRC12_BYPASS( 14, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 15, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 16, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC12_BYPASS( 17, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC12_BYPASS( 18, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC12_BYPASS( 19, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_SRC21_BYPASS( 20, 0, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 21, 0, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 22, 0, 2, mulw, 165, 15, 11 ); + TEST_RR_SRC21_BYPASS( 23, 1, 0, mulw, 143, 13, 11 ); + TEST_RR_SRC21_BYPASS( 24, 1, 1, mulw, 154, 14, 11 ); + TEST_RR_SRC21_BYPASS( 25, 2, 0, mulw, 165, 15, 11 ); + + TEST_RR_ZEROSRC1( 26, mulw, 0, 31 ); + TEST_RR_ZEROSRC2( 27, mulw, 0, 32 ); + TEST_RR_ZEROSRC12( 28, mulw, 0 ); + TEST_RR_ZERODEST( 29, mulw, 33, 34 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/rem.S b/isa/rv64um/rem.S new file mode 100644 index 0000000..e3248ff --- /dev/null +++ b/isa/rv64um/rem.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# rem.S +#----------------------------------------------------------------------------- +# +# Test rem instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, rem, 2, 20, 6 ); + TEST_RR_OP( 3, rem, -2, -20, 6 ); + TEST_RR_OP( 4, rem, 2, 20, -6 ); + TEST_RR_OP( 5, rem, -2, -20, -6 ); + + TEST_RR_OP( 6, rem, 0, -1<<63, 1 ); + TEST_RR_OP( 7, rem, 0, -1<<63, -1 ); + + TEST_RR_OP( 8, rem, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, rem, 1, 1, 0 ); + TEST_RR_OP(10, rem, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remu.S b/isa/rv64um/remu.S new file mode 100644 index 0000000..6946d0d --- /dev/null +++ b/isa/rv64um/remu.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remu.S +#----------------------------------------------------------------------------- +# +# Test remu instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remu, 2, 20, 6 ); + TEST_RR_OP( 3, remu, 2, -20, 6 ); + TEST_RR_OP( 4, remu, 20, 20, -6 ); + TEST_RR_OP( 5, remu, -20, -20, -6 ); + + TEST_RR_OP( 6, remu, 0, -1<<63, 1 ); + TEST_RR_OP( 7, remu, -1<<63, -1<<63, -1 ); + + TEST_RR_OP( 8, remu, -1<<63, -1<<63, 0 ); + TEST_RR_OP( 9, remu, 1, 1, 0 ); + TEST_RR_OP(10, remu, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remuw.S b/isa/rv64um/remuw.S new file mode 100644 index 0000000..334b5c5 --- /dev/null +++ b/isa/rv64um/remuw.S @@ -0,0 +1,41 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remuw.S +#----------------------------------------------------------------------------- +# +# Test remuw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remuw, 2, 20, 6 ); + TEST_RR_OP( 3, remuw, 2, -20, 6 ); + TEST_RR_OP( 4, remuw, 20, 20, -6 ); + TEST_RR_OP( 5, remuw, -20, -20, -6 ); + + TEST_RR_OP( 6, remuw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remuw, -1<<31, -1<<31, -1 ); + + TEST_RR_OP( 8, remuw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remuw, 1, 1, 0 ); + TEST_RR_OP(10, remuw, 0, 0, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/isa/rv64um/remw.S b/isa/rv64um/remw.S new file mode 100644 index 0000000..3ae8e3d --- /dev/null +++ b/isa/rv64um/remw.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# remw.S +#----------------------------------------------------------------------------- +# +# Test remw instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64U +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_RR_OP( 2, remw, 2, 20, 6 ); + TEST_RR_OP( 3, remw, -2, -20, 6 ); + TEST_RR_OP( 4, remw, 2, 20, -6 ); + TEST_RR_OP( 5, remw, -2, -20, -6 ); + + TEST_RR_OP( 6, remw, 0, -1<<31, 1 ); + TEST_RR_OP( 7, remw, 0, -1<<31, -1 ); + + TEST_RR_OP( 8, remw, -1<<31, -1<<31, 0 ); + TEST_RR_OP( 9, remw, 1, 1, 0 ); + TEST_RR_OP(10, remw, 0, 0, 0 ); + TEST_RR_OP(11, remw, 0xfffffffffffff897,0xfffffffffffff897, 0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END -- cgit v1.1 From 795c81a287bde70c6d8029a812f0a76e83823d68 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 22 Jun 2016 22:55:30 -0700 Subject: Mark RV32 tests as such @zhemao make sure to do "make run" in isa/ before committing --- isa/rv32ua/Makefrag | 2 +- isa/rv32um/Makefrag | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/isa/rv32ua/Makefrag b/isa/rv32ua/Makefrag index 9af6c7e..575dc6a 100644 --- a/isa/rv32ua/Makefrag +++ b/isa/rv32ua/Makefrag @@ -9,4 +9,4 @@ rv32ua_sc_tests = \ rv32ua_p_tests = $(addprefix rv32ua-p-, $(rv32ua_sc_tests)) rv32ua_v_tests = $(addprefix rv32ua-v-, $(rv32ua_sc_tests)) -spike_tests += $(rv32ua_p_tests) $(rv32ua_v_tests) +spike32_tests += $(rv32ua_p_tests) $(rv32ua_v_tests) diff --git a/isa/rv32um/Makefrag b/isa/rv32um/Makefrag index 50bffc8..1391c6a 100644 --- a/isa/rv32um/Makefrag +++ b/isa/rv32um/Makefrag @@ -10,4 +10,4 @@ rv32um_sc_tests = \ rv32um_p_tests = $(addprefix rv32um-p-, $(rv32um_sc_tests)) rv32um_v_tests = $(addprefix rv32um-v-, $(rv32um_sc_tests)) -spike_tests += $(rv32um_p_tests) $(rv32um_v_tests) +spike32_tests += $(rv32um_p_tests) $(rv32um_v_tests) -- cgit v1.1 From a33293e38b42ef0c8ef9f932a2721dfd5b95a622 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 6 Jul 2016 03:25:04 -0700 Subject: Update to new PTE format --- env | 2 +- isa/rv64mi/dirty.S | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/env b/env index 260b6ff..5c613fe 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 260b6fff32036dcfc8299aa21dd7cd443b18bb6a +Subproject commit 5c613fe43d1bc44e6ae408b5356c7d60d93a1ca0 diff --git a/isa/rv64mi/dirty.S b/isa/rv64mi/dirty.S index 9de358b..66ed5a0 100644 --- a/isa/rv64mi/dirty.S +++ b/isa/rv64mi/dirty.S @@ -44,7 +44,7 @@ RVTEST_CODE_BEGIN # Make sure R and D bits are set lw t0, page_table_2 - li t1, PTE_R | PTE_D + li t1, PTE_A | PTE_D and t0, t0, t1 bne t0, t1, die @@ -58,7 +58,7 @@ stvec_handler: bne TESTNUM, t1, 1f # Make sure R bit is set lw t0, page_table_1 - li t1, PTE_R + li t1, PTE_A and t0, t0, t1 bne t0, t1, die @@ -84,9 +84,9 @@ RVTEST_DATA_BEGIN TEST_DATA .align 12 -page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URX_SRX +page_table_1: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X dummy: .dword 0 .align 12 -page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_TYPE_URWX_SRWX +page_table_2: .dword (DRAM_BASE/RISCV_PGSIZE << PTE_PPN_SHIFT) | PTE_V | PTE_U | PTE_R | PTE_X | PTE_W RVTEST_DATA_END -- cgit v1.1 From d05da334979f92f10054a21fb5f98cac87484271 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 15:27:40 -0700 Subject: Delete unused benchmark --- benchmarks/sort/bmark.mk | 21 - benchmarks/sort/dataset.h | 2057 ------------------------------------ benchmarks/sort/sort.c | 255 ----- benchmarks/sort/sort.h | 57 - benchmarks/sort/sort_gendata.scala | 30 - benchmarks/sort/sort_main.c | 119 --- 6 files changed, 2539 deletions(-) delete mode 100644 benchmarks/sort/bmark.mk delete mode 100644 benchmarks/sort/dataset.h delete mode 100644 benchmarks/sort/sort.c delete mode 100644 benchmarks/sort/sort.h delete mode 100755 benchmarks/sort/sort_gendata.scala delete mode 100644 benchmarks/sort/sort_main.c diff --git a/benchmarks/sort/bmark.mk b/benchmarks/sort/bmark.mk deleted file mode 100644 index 1e76b68..0000000 --- a/benchmarks/sort/bmark.mk +++ /dev/null @@ -1,21 +0,0 @@ - -sort_c_src = \ - sort_main.c \ - sort.c \ - syscalls.c \ - -sort_riscv_src = \ - crt.S - -sort_c_objs = $(patsubst %.c, %.o, $(sort_c_src)) -sort_riscv_objs = $(patsubst %.S, %.o, $(sort_riscv_src)) - -sort_host_bin = sort.host -$(sort_host_bin): $(sort_c_src) - $(HOST_COMP) $^ -o $(sort_host_bin) - -sort_riscv_bin = sort.riscv -$(sort_riscv_bin): $(sort_c_objs) $(sort_riscv_objs) - $(RISCV_LINK) $(sort_c_objs) $(sort_riscv_objs) -o $(sort_riscv_bin) $(RISCV_LINK_OPTS) - -junk += $(sort_c_objs) $(sort_riscv_objs) $(sort_host_bin) $(sort_riscv_bin) diff --git a/benchmarks/sort/dataset.h b/benchmarks/sort/dataset.h deleted file mode 100644 index b04a193..0000000 --- a/benchmarks/sort/dataset.h +++ /dev/null @@ -1,2057 +0,0 @@ -// See LICENSE for license details. - -#define DATA_SIZE_SORT 1024 -float input_data_sort[1024] = { - 0.1757304, - 0.11887336, - 0.31508863, - 0.87429434, - 0.32998228, - 0.8617061, - 0.6609412, - 0.19959801, - 0.98842853, - 0.119490266, - 0.9348168, - 0.65575826, - 0.45825773, - 0.97723013, - 0.38904178, - 0.8539795, - 0.033690035, - 0.019101262, - 0.05240947, - 0.5234229, - 0.14557135, - 0.60703784, - 0.451209, - 0.6935377, - 0.44013077, - 0.33798885, - 0.89433634, - 0.49943197, - 0.23044586, - 0.121301234, - 0.8689161, - 0.593277, - 0.05368501, - 0.053545654, - 0.6745325, - 0.20875269, - 0.21469009, - 0.866569, - 0.49906075, - 0.84484196, - 0.7888443, - 0.6592707, - 0.83318657, - 0.5413125, - 0.32197475, - 0.69631076, - 0.32559925, - 0.49555874, - 0.5204319, - 0.6475523, - 0.80377436, - 0.70680165, - 0.32925904, - 0.95852894, - 0.39906925, - 0.7697948, - 0.59992826, - 0.37073708, - 0.20802563, - 0.42008877, - 0.841509, - 0.56534445, - 0.14839774, - 0.953649, - 0.5110267, - 0.6773647, - 0.098240376, - 0.9053897, - 0.751437, - 0.039974272, - 0.7747411, - 0.027303576, - 0.141011, - 0.06908399, - 0.3673455, - 0.5137753, - 0.72853225, - 0.11327422, - 0.7037065, - 0.8889426, - 0.63771373, - 0.378645, - 0.729311, - 0.011300623, - 0.715438, - 0.52502894, - 0.6201543, - 0.22995687, - 0.84622484, - 0.130499, - 0.73602027, - 0.01398164, - 0.574775, - 0.17442858, - 0.4388845, - 0.99323124, - 0.8751872, - 0.81291664, - 0.14141601, - 0.6210417, - 0.22579539, - 0.6596801, - 0.67486, - 0.8746262, - 0.42942703, - 0.26417083, - 0.5497203, - 0.029295504, - 0.8377925, - 0.54845864, - 0.06822199, - 0.5123382, - 0.16383338, - 0.25521147, - 0.6917526, - 0.79923284, - 0.90598094, - 0.42891055, - 0.9922046, - 0.84964263, - 0.46281397, - 0.13739341, - 0.86184824, - 0.48731065, - 0.3256001, - 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0.8950428, - 0.89547896, - 0.8955092, - 0.89642483, - 0.8972134, - 0.89802104, - 0.89859325, - 0.90036285, - 0.901283, - 0.9022279, - 0.90259147, - 0.9039292, - 0.9041813, - 0.9043403, - 0.90518177, - 0.9053897, - 0.90598094, - 0.9064294, - 0.90707433, - 0.90735143, - 0.90752304, - 0.9109975, - 0.91150093, - 0.91549635, - 0.91688704, - 0.9178185, - 0.9184999, - 0.91859597, - 0.9196396, - 0.9208161, - 0.92136437, - 0.9220043, - 0.9244678, - 0.92839295, - 0.93141407, - 0.93142414, - 0.93260723, - 0.93275, - 0.9342456, - 0.9346345, - 0.9348168, - 0.93528867, - 0.9394962, - 0.94084144, - 0.9410681, - 0.9422157, - 0.9423733, - 0.9434934, - 0.94446266, - 0.9457844, - 0.9472175, - 0.9475713, - 0.9488235, - 0.94918406, - 0.9504976, - 0.95205945, - 0.953649, - 0.9554563, - 0.956561, - 0.9566592, - 0.95678174, - 0.9576585, - 0.95803076, - 0.95816517, - 0.95852894, - 0.9608185, - 0.9613484, - 0.964232, - 0.9642434, - 0.9657087, - 0.9675673, - 0.97022545, - 0.9713107, - 0.97272724, - 0.97320575, - 0.97322446, - 0.97340614, - 0.97449046, - 0.97588015, - 0.97723013, - 0.9777305, - 0.9779671, - 0.97943527, - 0.98203504, - 0.9825553, - 0.98356473, - 0.9837329, - 0.9843066, - 0.9866693, - 0.98759604, - 0.98842853, - 0.9893386, - 0.99028367, - 0.9911397, - 0.9922046, - 0.9923581, - 0.9925594, - 0.99323124, - 0.9933987, - 0.99359006, - 0.9947238, - 0.99609894, - 0.9984882 -}; - diff --git a/benchmarks/sort/sort.c b/benchmarks/sort/sort.c deleted file mode 100644 index 9490361..0000000 --- a/benchmarks/sort/sort.c +++ /dev/null @@ -1,255 +0,0 @@ -// See LICENSE for license details. - -#include "sort.h" - -int -n_squared_sort (float * value, int * index, int len) -{ - int i, j; - - for (i = 0; i < len-1; i++) - { - for (j = 0; j < len-1; j++) - { - if (value[j] > value[j+1]) - { - double val_tmp; - int idx_tmp; - - val_tmp = value[j]; - value[j] = value[j+1]; - value[j+1] = val_tmp; - - idx_tmp = index[j]; - index[j] = index[j+1]; - index[j+1] = idx_tmp; - } - } - } - - return 0; -} - - -extern void* fake_malloc_radix(size_t size); - -int -radix_sort_tuples (int * value, int * index, int len, int radix_bits) -{ - int i, j; - int max, min; - int numBuckets = 1 << radix_bits; - int bitMask = numBuckets - 1; - int denShift; - - int * buckets = fake_malloc_radix ((numBuckets + 2) * sizeof(int)); - int * copy1_value = fake_malloc_radix (sizeof(int) * len); - int * copy1_index = fake_malloc_radix (sizeof(int) * len); - int * copy2_value = fake_malloc_radix (sizeof(int) * len); - int * copy2_index = fake_malloc_radix (sizeof(int) * len); - int * tmp_value; - int * tmp_index; - - max = value[0]; - min = value[0]; - for (i = 0; i < len; i++) { - copy1_value[i] = value[i]; - copy1_index[i] = index[i]; - if (max < value[i]) { - max = value[i]; - } - if (min > value[i]) { - min = value[i]; - } - } - min = -min; - max += min; - - for (i = 0; i < len; i++) - { - copy1_value[i] += min; - } - - denShift = 0; - for (i = 0; max != 0; max = max / numBuckets, i++) - { - for (j = 0; j < numBuckets + 2; j++) - { - buckets[j] = 0; - } - - buckets += 2; - - for (j = 0; j < len; j++) - { - int myBucket = (int) (((int) copy1_value[j]) >> denShift) & bitMask; - buckets[myBucket]++; - } - - for (j = 1; j < numBuckets; j++) - { - buckets[j] += buckets[j-1]; - } - - buckets--; - - for (j = 0; j < len; j++) - { - int myBucket = (int) (((int) copy1_value[j]) >> denShift) & bitMask; - int index = buckets[myBucket]++; - copy2_value[index] = copy1_value[j]; - copy2_index[index] = copy1_index[j]; - } - - buckets--; - denShift += radix_bits; - - tmp_value = copy1_value; - copy1_value = copy2_value; - copy2_value = tmp_value; - - tmp_index = copy1_index; - copy1_index = copy2_index; - copy2_index = tmp_index; - } - - max = copy1_value[0]; - for (i = 0; i < len; i++) { - if (max < copy1_value[i]) { - max = copy1_value[i]; - } - } - - for (i = 0; i < len; i++) - { - copy1_value[i] -= min; - } - - for (i = 0; i < len; i++) - { - value[i] = copy1_value[i]; - index[i] = copy1_index[i]; - } - - return 0; -} - -int -insertion_sort (float * value, int * index, int len) -{ - int i; - - for (i = 1; i < len; i++) - { - double current; - int cur_index; - int empty; - - current = value[i]; - cur_index = index[i]; - empty = i; - - while (empty > 0 && current < value[empty-1]) - { - value[empty] = value[empty-1]; - index[empty] = index[empty-1]; - empty--; - } - - value[empty] = current; - index[empty] = cur_index; - } - - return 0; -} - - -int -partition (float * array, int * index, int low, int high) -{ - int left, right, mid; - int pivot; - float cur; - int idx; - - mid = (low + high) / 2; - left = low; - right = high; - - /* choose pivot as median of 3: low, high, and mid */ - if ((array[low] - array[mid]) * (array[high] - array[low]) >= 0) - pivot = low; - else if ((array[mid] - array[low]) * (array[high] - array[mid]) >= 0) - pivot = mid; - else - pivot = high; - - /* store value,index at the pivot */ - cur = array[pivot]; - idx = index[pivot]; - - /* swap pivot with the first entry in the list */ - array[pivot] = array[low]; - array[low] = cur; - - index[pivot] = array[pivot]; - index[low] = idx; - - /* the quicksort itself */ - while (left < right) - { - while (array[left] <= cur && left < high) - left++; - while (array[right] > cur) - right--; - if (left < right) - { - float tmp_val; - int tmp_idx; - - tmp_val = array[right]; - array[right] = array[left]; - array[left] = tmp_val; - - tmp_idx = index[right]; - index[right] = index[left]; - index[left] = tmp_idx; - } - } - - /* pivot was in low, but now moves into position at right */ - array[low] = array[right]; - array[right] = cur; - - index[low] = index[right]; - index[right] = idx; - - return right; -} - - -int -quicksort_inner (float * array, int * index, int low, int high) -{ - int pivot; - int length = high - low + 1; - - if (high > low) - { - if (length > MAX_THRESH) { - pivot = partition (array, index, low, high); - quicksort_inner (array, index, low, pivot-1); - quicksort_inner (array, index, pivot+1, high); - } - } - - return 0; -} - -int quicksort (float * array, int * index, int len) -{ - quicksort_inner (array, index, 0, len-1); - insertion_sort (array, index, len); - - return 0; -} diff --git a/benchmarks/sort/sort.h b/benchmarks/sort/sort.h deleted file mode 100644 index 149744a..0000000 --- a/benchmarks/sort/sort.h +++ /dev/null @@ -1,57 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include - -#define USE_N_SQUARED_SORT - -#define FAKE_MALLOC_INIT(words, name) \ - uint32_t heap_##name[words]; \ - const size_t max_alloc_##name = (words) * sizeof(uint32_t); \ - size_t cur_pos_##name; \ - void* fake_malloc_##name( size_t size ) \ - { \ - static bool init = false; \ - if(!init) { \ - cur_pos_##name = 0; \ - init = true; \ - } \ - if(cur_pos_##name < (words)) { \ - void *ptr = (void*) &heap_##name[cur_pos_##name]; \ - cur_pos_##name += size & ~((uint32_t)3) + 1; \ - return ptr; \ - } else { \ - return NULL; \ - } \ - } - - - -#ifndef _TAV_SORT_H_ -#define _TAV_SORT_H_ - - -int -n_squared_sort (float * value, int * index, int len); - -int -radix_sort_tuples (int * value, int * index, int len, int radix_bits); - -int -insertion_sort (float * value, int * index, int len); - -int -quicksort (float * array, int * index, int len); - -/* This defines the length at quicksort switches to insertion sort */ -#ifndef MAX_THRESH -#define MAX_THRESH 10 -#endif - -#ifndef RADIX_BITS -#define RADIX_BITS (8) -#endif - - -#endif /* _TAV_SORT_H_ */ diff --git a/benchmarks/sort/sort_gendata.scala b/benchmarks/sort/sort_gendata.scala deleted file mode 100755 index 2f44074..0000000 --- a/benchmarks/sort/sort_gendata.scala +++ /dev/null @@ -1,30 +0,0 @@ -#!/usr/bin/env scala - -import scala.util.Sorting - -if(args.size < 2) { - println("Usage: sort_gendata <# elements> <# trials>") - System.exit(1) -} - -val size = args(0).toInt -val trials = args(1).toInt - -def rand_array(size: Int) = { - var r = new scala.util.Random - Array.fill(size) { r.nextFloat() } -} - -def print_array(name: String, size: Int, arr: Array[Float]) { - println("float "+name+"["+size+"] = {") - for(i <- 0 to size-2) - println(" "+arr(i)+",") - println(" "+arr(size-1)+"\n};\n") -} - -println("#define DATA_SIZE_SORT " + size) -println("#define TRIALS_SORT " + trials) - -val a = rand_array(size * trials) - -print_array("input_data_sort", size * trials, a) diff --git a/benchmarks/sort/sort_main.c b/benchmarks/sort/sort_main.c deleted file mode 100644 index 29b46c5..0000000 --- a/benchmarks/sort/sort_main.c +++ /dev/null @@ -1,119 +0,0 @@ -// See LICENSE for license details. - -// **************************************************************************** -// sort benchmark from DARPA PERFECT TAV suite -// ---------------------------------------------------------------------------- -#include "sort.h" -#include "util.h" -#include "dataset.h" - - -// Need 7 times the input size for: input data, indices, -// four copies, and buckets. -FAKE_MALLOC_INIT( (8 * DATA_SIZE_SORT * TRIALS_SORT), radix ) - - -#if defined(USE_N_SQUARED_SORT) -const char* algo = "N_SQUARED"; -#elif defined(USE_RADIX_SORT) -const char* algo = "RADIX"; -#elif defined(USE_INSERTION_SORT) -const char* algo = "INSERTION"; -#else -const char* algo = "QUICKSORT"; -#endif - - - -int main( int argc, char* argv[] ) -{ - int err; - - int* index = fake_malloc_radix (sizeof(int) * DATA_SIZE_SORT * TRIALS_SORT); - for(int trial = 0; trial < TRIALS_SORT; trial++) - for ( int i = 0; i < DATA_SIZE_SORT; i++ ) - index[i + (DATA_SIZE_SORT * trial)] = i; - -#ifdef PREALLOCATE - // Access every element of input_data_sort to make sure it's in cache - // (or at least that as much as possible of its beginning is). - float sum = 0; - for(int i = (DATA_SIZE_SORT * TRIALS_SORT)-1; i >= 0; i--) { - sum += input_data_sort[i]; - } - if(sum < 0.1) - return 1; - - const bool prealloc = true; -#else - const bool prealloc = false; -#endif - - setStats(1); - -#define read_csr_safe(reg) ({ long __tmp = 0; \ - asm volatile ("csrr %0, " #reg : "+r"(__tmp)); \ - __tmp; }) - - - long cycles_total = 0; - long instret_total = 0; - - for(int i = 0; i < TRIALS_SORT; i++) { - long cycles = read_csr_safe(cycle); - long instret = read_csr_safe(instret); - - float* input_data_trial = &input_data_sort[DATA_SIZE_SORT * i]; - int* index_trial = &index[DATA_SIZE_SORT * i]; - -#if defined(USE_N_SQUARED_SORT) - err = n_squared_sort ( input_data_trial, index_trial, DATA_SIZE_SORT ); -#elif defined(USE_RADIX_SORT) - err = radix_sort_tuples ( (int *) input_data_trial, index_trial, DATA_SIZE_SORT, RADIX_BITS ); -#elif defined(USE_INSERTION_SORT) - err = insertion_sort ( input_data_trial, index_trial, DATA_SIZE_SORT ); -#else - err = quicksort ( input_data_trial, index_trial, DATA_SIZE_SORT ); -#endif - - cycles_total += read_csr_safe(cycle) - cycles; - instret_total += read_csr_safe(instret) - instret; - } - - setStats(0); - - printf("DONE SORTING.\n", 0); - - // Validate results - err = 0; - for(int trial = 0; trial < TRIALS_SORT; trial++) - { - float* input_data_trial = &input_data_sort[DATA_SIZE_SORT * trial]; - int* index_trial = &index[DATA_SIZE_SORT * trial]; - - for(int i = 0; i < DATA_SIZE_SORT-1; i++) - { - if((unsigned int) input_data_trial[i] > (unsigned int) input_data_trial[i+1]) - { - err = i; - for(int j = 0; j < DATA_SIZE_SORT; j++) - printf("TRIAL %d, element %d:\t%d\n", trial, j, input_data_trial[j]); - break; - } - } - } - - printf("sort_cycles = %ld\n", cycles_total/TRIALS_SORT); - printf("sort_instret = %d\n", instret_total/TRIALS_SORT); - printf("sort_size = %d\n", DATA_SIZE_SORT); - printf("sort_trials = %d\n", TRIALS_SORT); - printf("sort_algo = %s\n", algo); - printf("sort_radix_bits = %d\n", RADIX_BITS); - printf("sort_prealloc = %s\n", prealloc ? "true" : "false"); - printf("sort_err = %d\n", err); - - return err; -} - - - -- cgit v1.1 From aff36b0963e6eee63906b3d8622be5a98ba27a43 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 19:28:47 -0700 Subject: Don't use FPU in benchmarks that don't need to use the FPU --- benchmarks/common/crt.S | 27 ++++++++++++--------------- benchmarks/common/syscalls.c | 3 --- benchmarks/common/util.h | 2 -- benchmarks/dhrystone/dhrystone.h | 2 +- 4 files changed, 13 insertions(+), 21 deletions(-) diff --git a/benchmarks/common/crt.S b/benchmarks/common/crt.S index 7c8fc19..2dda05b 100644 --- a/benchmarks/common/crt.S +++ b/benchmarks/common/crt.S @@ -50,29 +50,26 @@ _start: li x30,0 li x31,0 - li t0, MSTATUS_FS; csrs mstatus, t0 # enable FPU - li t0, MSTATUS_XS; csrs mstatus, t0 # enable accelerator + # enable FPU and accelerator if present + li t0, MSTATUS_FS | MSTATUS_XS + csrs mstatus, t0 -#ifdef __riscv64 + # make sure XLEN agrees with compilation choice csrr t0, misa - # make sure processor supports RV64 if this was compiled for RV64 +#ifdef __riscv64 bltz t0, 1f +#else + bgez t0, 1f +#endif li a0, 1234 j tohost_exit 1: -#endif - - csrr t0, mstatus - li t1, MSTATUS_XS - and t1, t0, t1 - sw t1, have_vec, t2 - - ## if that didn't stick, we don't have a FPU, so don't initialize it - li t1, MSTATUS_FS - and t1, t0, t1 - beqz t1, 1f #ifdef __riscv_hard_float + # initialize FPU if we have one + andi t0, t0, 1 << ('f' - 'a') + beqz t0, 1f + fssr x0 fmv.s.x f0, x0 fmv.s.x f1, x0 diff --git a/benchmarks/common/syscalls.c b/benchmarks/common/syscalls.c index 0a43878..316f2fe 100644 --- a/benchmarks/common/syscalls.c +++ b/benchmarks/common/syscalls.c @@ -11,9 +11,6 @@ #define SYS_exit 93 #define SYS_stats 1234 -// initialized in crt.S -int have_vec; - extern volatile uint64_t tohost; extern volatile uint64_t fromhost; diff --git a/benchmarks/common/util.h b/benchmarks/common/util.h index c35bf7c..22f81cf 100644 --- a/benchmarks/common/util.h +++ b/benchmarks/common/util.h @@ -35,8 +35,6 @@ extern void setStats(int enable); #include -extern int have_vec; - #define static_assert(cond) switch(0) { case 0: case !!(long)(cond): ; } static void printArray(const char name[], int n, const int arr[]) diff --git a/benchmarks/dhrystone/dhrystone.h b/benchmarks/dhrystone/dhrystone.h index 89616af..e350c17 100644 --- a/benchmarks/dhrystone/dhrystone.h +++ b/benchmarks/dhrystone/dhrystone.h @@ -412,7 +412,7 @@ struct tms time_info; #endif /* TIME */ -#define Mic_secs_Per_Second 1000000.0 +#define Mic_secs_Per_Second 1000000 #define NUMBER_OF_RUNS 500 /* Default number of runs */ #ifdef NOSTRUCTASSIGN -- cgit v1.1 From 3dc00e7b04834f862a074ac8822892e1ecfc009c Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 7 Jul 2016 19:29:03 -0700 Subject: Update WFI test for priv v1.9 --- env | 2 +- isa/rv32mi/Makefrag | 1 - isa/rv32mi/wfi.S | 8 -------- isa/rv64si/wfi.S | 5 +++-- 4 files changed, 4 insertions(+), 12 deletions(-) delete mode 100644 isa/rv32mi/wfi.S diff --git a/env b/env index 5c613fe..92fb0bd 160000 --- a/env +++ b/env @@ -1 +1 @@ -Subproject commit 5c613fe43d1bc44e6ae408b5356c7d60d93a1ca0 +Subproject commit 92fb0bd7d7d2723f90896bb351f5cdb0eb36b73b diff --git a/isa/rv32mi/Makefrag b/isa/rv32mi/Makefrag index 9aeb12d..c8fbcf4 100644 --- a/isa/rv32mi/Makefrag +++ b/isa/rv32mi/Makefrag @@ -12,7 +12,6 @@ rv32mi_sc_tests = \ scall \ sbreak \ shamt \ - wfi \ rv32mi_mc_tests = \ ipi \ diff --git a/isa/rv32mi/wfi.S b/isa/rv32mi/wfi.S deleted file mode 100644 index d5cb3cb..0000000 --- a/isa/rv32mi/wfi.S +++ /dev/null @@ -1,8 +0,0 @@ -# See LICENSE for license details. - -#include "riscv_test.h" -#undef RVTEST_RV64S -#define RVTEST_RV64S RVTEST_RV32M -#define __MACHINE_MODE - -#include "../rv64si/wfi.S" diff --git a/isa/rv64si/wfi.S b/isa/rv64si/wfi.S index 8e56909..0302034 100644 --- a/isa/rv64si/wfi.S +++ b/isa/rv64si/wfi.S @@ -13,9 +13,10 @@ RVTEST_RV64S RVTEST_CODE_BEGIN - # Make sure wfi doesn't stall if an interrupt is pending, even if masked + # Make sure wfi doesn't halt the hart, even if interrupts are disabled csrc sstatus, SSTATUS_SIE - csrs sip, MIP_SSIP + csrs sie, SIP_SSIP + csrs sip, SIP_SSIP wfi RVTEST_PASS -- cgit v1.1