| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-08-17 | making mtvec_handler global (#150) | Srivatsa Yogendra | 1 | -0/+1 | |
| 2017-05-17 | Manually assemble bad shift amount, since assembler rejects | Andrew Waterman | 1 | -1/+1 | |
| Resolves #51 | |||||
| 2017-04-07 | Remove defunct IPI tests | Andrew Waterman | 2 | -10/+0 | |
| 2016-07-29 | Add RV32 RVC and breakpoint tests | Andrew Waterman | 2 | -1/+10 | |
| 2016-07-22 | Move rv32mi dirty bit test to rv32si | Andrew Waterman | 2 | -11/+0 | |
| 2016-07-07 | Update WFI test for priv v1.9 | Andrew Waterman | 2 | -9/+0 | |
| 2016-04-30 | ERET -> xRET; new memory map | Andrew Waterman | 2 | -10/+1 | |
| For now, we no longer build hex files, because the programs don't start at address 0. This decision will likely be revisited. | |||||
| 2016-03-10 | Add missing rv32mi/rv32si tests | Andrew Waterman | 4 | -0/+28 | |
| 2016-03-03 | Some S-mode tests really only belong in M-mode | Andrew Waterman | 4 | -8/+50 | |
| 2015-07-05 | New M-mode timers | Andrew Waterman | 1 | -4/+3 | |
| 2015-04-03 | Run RV32 tests on spike with --isa=RV32 | Andrew Waterman | 1 | -0/+2 | |
| 2015-03-25 | split out S-mode tests and M-mode tests | Yunsup Lee | 9 | -0/+81 | |
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index : rocket-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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