Age | Commit message (Collapse) | Author | Files | Lines |
|
* Test debugging multiple spikes in a daisy chain.
* Hugely speed up rbb_daisychain.
Now 2 dual-hart spikes are less than 4x slower than a single dual-hart
spike.
* WIP
* Test daisy chained homogeneous spike instances.
For OpenOCD, this means we're checking that we can talk to multiple
TAPs. Next up is heterogeneous testing.
* Enable Sv48Test.
Didn't mean to disable it with this commit.
* Test authentication again.
Another change I hadn't meant to push...
|
|
* Add FreeRTOS smoke tests.
Make sure that OpenOCD can access all threads in a FreeRTOS binary on
single-hart RV32 and RV64.
* Also test `-rtos FreeRTOS`.
|
|
It's faster to figure out there that the test is going to N/A.
|
|
|
|
This allows the vast majority of these tests to work with compilers that
don't support the V extension yet, which is helpful for people who
aren't using a vector branch of the compiler.
Specifically, this will hopefully allow us to run regression tests
against OpenOCD on every change, per
https://github.com/riscv/riscv-openocd/pull/563.
|
|
This fixes an intermitten failure when running these tests.
|
|
As of tomorrow that feature is officially no longer supported in
OpenOCD, so stop testing it.
|
|
HiFiveUnleashed-flash fails som address translation tests. Possibly that
would be fixed when https://github.com/riscv/riscv-tests/pull/313
merges.
|
|
|
|
This test would have found
https://github.com/riscv/riscv-openocd/issues/559.
|
|
|
|
|
|
|
|
Addresses #289.
|
|
This is now required to use `-rtos riscv`.
Addresses the aside mentioned in #287.
|
|
|
|
Make sure OpenOCD cooperates when a user sets a trigger by writing
tselect/tdata* directly.
|
|
* WIP
* WIP
* Vector test seems to work well with spike.
* Check a0 in case the program didn't work right.
* Return not applicable if compile doesn't support V
|
|
* Add a basic semihosting test.
* Need to configure semihosting on each target.
* WIP
* Parse "cannot insert breakpoint" message.
Also use sys.exit instead of exit, per new pylint's suggestion.
|
|
Also use sys.exit instead of exit, per new pylint's suggestion.
|
|
Test the behavior described in
https://github.com/riscv/riscv-openocd/issues/76.
|
|
|
|
* Improve address translation tests.
Check that the mode we're testing is supported by hardware before
running the test.
Test with high address bits set, which catches a bug in OpenOCD.
* Turn off PMP for address translation test.
Otherwise it doesn't pass on HiFive Unleashed.
* Run TranslateTest on random hart.
Once https://github.com/riscv/riscv-openocd/pull/459 merges that will work.
|
|
Otherwise it only passes intermittently when I change _start, which is
very confusing.
|
|
This was changed by https://github.com/riscv/riscv-isa-sim/pull/417
|
|
This saves a few seconds every time I run any test.
|
|
Also fix bug in parsing nan.
|
|
|
|
* WIP
* Add vector register smoketest.
Also redo the gdb value parsing code to accommodate the more complicated
way that vector registers look.
* Test vector access a little more thoroughly.
* Revert unnecessary changes.
|
|
This way if you end up reading a value that you suspect might be coming
from another hart/register, you can clearly see where it came from.
|
|
If it's in the path, at least. This way you get human readable assembly
in the log instead of hex values.
|
|
|
|
This catches more corner cases where this may be a problem.
|
|
* WIP
* Smoke test virtual address support.
Tests sv32, sv39, and sv48. Only explicitly tests 4K pages, but uses as
large as possible pages to 1:1 map the rest of RAM so those sizes do get
minimal coverage as well.
|
|
`make` now takes 31s, `make all` takes 1m53s.
The new CheckMisa test ensures that the misa value specified in the
configuration is correct.
|
|
|
|
* Improve parallellism in debug test Makefile
Now each test is an individual make target, so you can get the most out
of however many cores you have. On my 12-core system, `make` went from
2m45s to 42s, and `make all` went from `3m25s` to `2m39s`.
If you have few cores, this change may actually slow things down a bit,
because ExamineTarget is run for every gdbserver.py invocation.
* Remove test target.
|
|
This binary comes from
https://github.com/timsifive/freedom-u540-c000-bootloader/tree/board_setup2,
which will hopefully be accepted upstream.
|
|
The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.
|
|
* Parse inf/nan floats.
* Enable mstatus.fs in SimpleF18Test
Also accept "unable to fetch" message when FPRs aren't supported.
* Add config files for HiFive Unleashed.
* Add configs to flash HiFive Unleashed.
All tests pass.
|
|
The latest OpenOCD doesn't need (nor support) this anymore.
|
|
Hopefully this is enough information that I can simply point people who
submit OpenOCD changes to it, and they can run the tests themselves.
|
|
Instead of relying on $RISCV. Using $RISCV was common in the early
days, but nowadays many tools are simply installed alongside the rest of
the system.
|
|
* Let the debugger enable mstatus.F if necessary.
* Ignore (some) gdb debug output.
* Increase timeout.
* Make newer version of pylint happy.
|
|
|
|
|
|
* Parse floats the way mainline gdb prints them.
For 64-bit floats, it shows both float and double results. Now more
tests pass using mainline gdb.
* Disable ANSI when talking to gdb.
Helps more tests pass with mainline gdb.
* Parse {float=...,double=...} in "info registers"
Makes tests work better with mainline gdb.
|
|
Also work with the new command line options that were renamed in
https://github.com/riscv/riscv-isa-sim/pull/299
|
|
|
|
Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
|