| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-05-18 | Fix MulticoreRunHaltStepiTest | Tim Newsome | 2 | -23/+46 | |
| The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so. | |||||
| 2018-05-14 | Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single | Megan Wachs | 2 | -21/+11 | |
| 2018-05-14 | Make DownloadTest properly park other harts. | Tim Newsome | 2 | -5/+9 | |
| 2018-05-14 | debug: remove some unintentionally added newlines | Megan Wachs | 1 | -2/+0 | |
| 2018-05-14 | debug: Fixing the non-RTOS behavior for DownloadTest | Megan Wachs | 1 | -7/+16 | |
| 2018-05-11 | debug: mark more tests as single-hart tests | Megan Wachs | 1 | -6/+13 | |
| 2018-05-11 | debug: output some more useful info into the post-mortem data | Megan Wachs | 1 | -0/+5 | |
| 2018-04-30 | Fix formatting to make pylint happy. | Tim Newsome | 1 | -5/+6 | |
| 2018-04-27 | debug: need to clear satp before changing privdebug-clear-satp | Megan Wachs | 1 | -0/+7 | |
| ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness. | |||||
| 2018-04-27 | Merge pull request #125 from riscv/debug-delete-sim | Megan Wachs | 1 | -17/+0 | |
| Delete E300Sim.py | |||||
| 2018-04-27 | debug: add missing align directive on trap_entrytrap_entry_align-1 | Megan Wachs | 1 | -0/+1 | |
| 2018-04-24 | Fix race when making logs directory | Tim Newsome | 1 | -1/+5 | |
| 2018-04-19 | Delete E300Sim.pydebug-delete-sim | Megan Wachs | 1 | -17/+0 | |
| This file is wrong (the .cfg file isn't right) and not used by anything. | |||||
| 2018-04-09 | Compute gdb command timeout based on ops estimate | Tim Newsome | 2 | -14/+18 | |
| The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122. | |||||
| 2018-04-02 | Use `gdb_report_register_access_error enable` | Tim Newsome | 4 | -0/+6 | |
| 2018-03-27 | Test debug authentication. | Tim Newsome | 4 | -3/+19 | |
| Also halt instead of reset spike targets, which tests a more complicated code path. | |||||
| 2018-03-23 | Print log filename at the end of the log. | Tim Newsome | 1 | -0/+1 | |
| This makes it much easier to look at a log if you see a failure scrolling by on your terminal. | |||||
| 2018-03-01 | Test debugging with/without a program buffer | Tim Newsome | 5 | -5/+10 | |
| 2018-03-01 | Ensure an error when reading a non-existent CSR. | Tim Newsome | 5 | -0/+29 | |
| 2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 3 | -10/+9 | |
| 2018-02-07 | Link scripts shouldn't be executable. | Tim Newsome | 1 | -0/+0 | |
| 2018-01-08 | Deal with gdb reporting pmpcfg0 not existing. | Tim Newsome | 2 | -3/+16 | |
| It's an optional register. | |||||
| 2018-01-05 | Add test for multicore failure | Tim Newsome | 2 | -5/+40 | |
| Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1. | |||||
| 2017-12-27 | Test FPRs that aren't XLEN in size. | Tim Newsome | 6 | -8/+20 | |
| Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110 | |||||
| 2017-12-21 | Add all-tests target. | Tim Newsome | 1 | -1/+3 | |
| I hope to use this in riscv-tools' regression.sh. | |||||
| 2017-12-20 | Remove `set arch riscv:rv%d` | Tim Newsome | 1 | -1/+0 | |
| gdb gets target XLEN from register width now, so this is taken care of automatically. | |||||
| 2017-12-20 | Verify that F18 does not exist on FPU-less targets | Tim Newsome | 1 | -17/+20 | |
| 2017-12-12 | Display env variables used when invoking OpenOCD | Tim Newsome | 1 | -1/+6 | |
| This makes it a little easier to just cut and paste from the log when reproducing a failure. (The port number still needs changing though.) | |||||
| 2017-12-01 | Ensure there are no unnamed registers. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-30 | Clean up VcsSim init() | Tim Newsome | 1 | -2/+12 | |
| Use a unique log file, so you can run multiple instances at once. Add time out to waiting for the simulator to be ready. | |||||
| 2017-11-27 | Rename sbadaddr to satp | Andrew Waterman | 1 | -3/+3 | |
| 2017-11-19 | Ensure log file is fully written before reading it | Tim Newsome | 1 | -0/+1 | |
| Fixes --print-failures sometimes not actually printing out details about failures. | |||||
| 2017-11-19 | Make pylint happy. | Tim Newsome | 3 | -12/+16 | |
| 2017-11-17 | debug: Fix the XLEN command line checkxlen_fix | Megan Wachs | 1 | -7/+8 | |
| 2017-11-16 | Debug: Use the --32 and --64 command line arguments (#97) | Megan Wachs | 3 | -10/+17 | |
| * Debug: Actually use the --32 and --64 command line arguments * debug: make XLEN mismatch message clearer | |||||
| 2017-11-16 | Disable PMP for PrivRw test. | Tim Newsome | 1 | -0/+5 | |
| 2017-11-15 | Clarify PrivTest detail. | Tim Newsome | 1 | -0/+2 | |
| 2017-11-02 | Add --print-log-names to print temp log names ASAP | Tim Newsome | 2 | -5/+17 | |
| When not passed, they are no longer printed out. | |||||
| 2017-11-02 | Ensure gdb connection failures end up in main log. | Tim Newsome | 1 | -9/+18 | |
| 2017-11-02 | debug: Need to apply remotetimeout before connecting to remote target (#94) | Megan Wachs | 1 | -6/+7 | |
| * debug: Need to apply remotetimeout before connecting to remote target * debug: whitespace cleanup | |||||
| 2017-11-01 | Make pylint 1.6.5 happy. | Tim Newsome | 4 | -6/+5 | |
| 2017-11-01 | Test register aliases in the simple register tests | Tim Newsome | 1 | -9/+17 | |
| 2017-11-01 | Fix MulticoreRegTest. | Tim Newsome | 2 | -59/+65 | |
| This test would fail intermittently if gdb on the first hart managed to set a breakpoint, resume, halt, and clear the breakpoint before the second hart got a chance to resume. | |||||
| 2017-10-31 | Temporarily comment out MulticoreRegTest due to flakiness. | Richard Xia | 1 | -57/+58 | |
| 2017-10-24 | Increase dual-core RV64 timeouts. | Tim Newsome | 2 | -2/+2 | |
| I need this for CompareSections to pass when I instrument spike to be really slow. | |||||
| 2017-10-19 | Get helpful gdb output in MemTestBlock. | Tim Newsome | 1 | -1/+4 | |
| 2017-10-12 | Pay attention to server_timeout_sec | Tim Newsome | 1 | -2/+3 | |
| Fixes #83. | |||||
| 2017-10-04 | Resurrect priv tests. | Tim Newsome | 1 | -52/+51 | |
| 2017-10-04 | Merge pull request #79 from riscv/multigdb | Tim Newsome | 13 | -96/+236 | |
| Multigdb support | |||||
| 2017-09-29 | Make ExamineTarget multi-core aware. | Tim Newsome | 1 | -18/+23 | |
| Now on multi-core targets it only runs once, wasting less time. | |||||
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index : rocket-tools/riscv-tests.git | |
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