| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2018-11-16 | Make pylint happy. | Tim Newsome | 1 | -3/+6 | |
| 2018-11-14 | Merge pull request #165 from riscv/flash | Tim Newsome | 7 | -18/+103 | |
| Tweak debug tests to run out of flash. | |||||
| 2018-11-14 | Cleanup and renamed test flag to invalid_memory_returns_zero | cgsfv | 4 | -6/+6 | |
| 2018-11-13 | Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix | cgsfv | 4 | -2/+59 | |
| 2018-11-12 | Simpler/more idiomatic way to keep string on stack | Tim Newsome | 1 | -4/+1 | |
| 2018-10-31 | Add HiFive1-flash target configuration. | Tim Newsome | 2 | -0/+59 | |
| 2018-10-31 | Fix remaining tests to work from flash: | Tim Newsome | 2 | -6/+17 | |
| TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint. | |||||
| 2018-10-29 | Almost all tests pass with HiFive1-flash | Tim Newsome | 2 | -4/+13 | |
| Only TriggerDmode still fails. | |||||
| 2018-10-29 | Tweak debug tests to run out of flash. | Tim Newsome | 4 | -8/+17 | |
| Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant. | |||||
| 2018-10-24 | Merge branch 'TriggerLoadAddressInstant' | Tim Newsome | 1 | -12/+1 | |
| 2018-10-24 | Re-enable TriggerStoreAddressInstant | Tim Newsome | 1 | -12/+1 | |
| Gdb and OpenOCD were fixed so we don't have to accept broken behavior anymore. | |||||
| 2018-10-05 | Make HwWatchpoint test fail on incorrect result.hw_watchpoint | Tim Newsome | 3 | -7/+10 | |
| Also tiny cleanups, making pylint happy. | |||||
| 2018-10-03 | Added tests for hw and sw watchpoints | cgsfv | 3 | -0/+88 | |
| 2018-09-13 | Assert if HiFive1 program is too large. | Tim Newsome | 1 | -0/+2 | |
| 2018-09-13 | Put debug test stack in data instead of text | Tim Newsome | 1 | -0/+1 | |
| 2018-09-03 | Merge pull request #156 from riscv/PrivChange | Tim Newsome | 1 | -27/+26 | |
| Reset address translation/perms before PrivChange | |||||
| 2018-08-31 | Fix CustomRegisterTest. | Tim Newsome | 2 | -5/+6 | |
| gdb in riscv-tools doesn't automatically create a "custom" group like mainline gdb does. | |||||
| 2018-08-29 | Add test case for `riscv expose_custom`. | Tim Newsome | 12 | -0/+55 | |
| Only works against spike, where I've implemented some custom debug registers to test against. | |||||
| 2018-08-28 | Reset address translation/perms before PrivChange | Tim Newsome | 1 | -27/+26 | |
| We already did this for PrivTest. Hopefully solves #155, but I haven't been able to reproduce it. | |||||
| 2018-08-27 | Neuter TriggerStoreAddressInstant | Tim Newsome | 1 | -1/+13 | |
| Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful. | |||||
| 2018-08-27 | Make pylint happy. | Tim Newsome | 1 | -1/+2 | |
| 2018-08-25 | Temporarily disabling PrivChange test | Andrew Waterman | 1 | -22/+23 | |
| @timsifive we are debugging intermittent failures. | |||||
| 2018-08-23 | Make pylint happy with change d1d2d953b5016b465. | Tim Newsome | 2 | -3/+4 | |
| 2018-08-23 | Get all of the log into the final log file | Tim Newsome | 1 | -6/+20 | |
| This allows me to see the final valgrind output on OpenOCD, so I can watch for memory leaks when using --server_cmd "valgrind --leak-check=full openocd". | |||||
| 2018-08-23 | Merge pull request #153 from dmitryryzhov/rtos-switch-active-thread | Tim Newsome | 1 | -0/+28 | |
| Add debug test, which checks that openocd correctly switch active thread on any hart halt. | |||||
| 2018-08-22 | Disable MulticoreRunHaltStepiTest | Tim Newsome | 1 | -52/+52 | |
| It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification | |||||
| 2018-08-22 | Add debug test, which checks that openocd correctly switch active thread on ↵ | Dmitry Ryzhov | 1 | -0/+28 | |
| any hart halt. | |||||
| 2018-08-13 | Add jump/hbreak test. | Tim Newsome | 1 | -0/+23 | |
| 2018-07-03 | rwatch/watch on explicit address | Tim Newsome | 1 | -2/+4 | |
| Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use. | |||||
| 2018-06-18 | Add reproduce line to the end of debug test logs | Tim Newsome | 1 | -0/+2 | |
| 2018-05-18 | Fix MulticoreRunHaltStepiTest | Tim Newsome | 2 | -23/+46 | |
| The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so. | |||||
| 2018-05-14 | Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-single | Megan Wachs | 2 | -21/+11 | |
| 2018-05-14 | Make DownloadTest properly park other harts. | Tim Newsome | 2 | -5/+9 | |
| 2018-05-14 | debug: remove some unintentionally added newlines | Megan Wachs | 1 | -2/+0 | |
| 2018-05-14 | debug: Fixing the non-RTOS behavior for DownloadTest | Megan Wachs | 1 | -7/+16 | |
| 2018-05-11 | debug: mark more tests as single-hart tests | Megan Wachs | 1 | -6/+13 | |
| 2018-05-11 | debug: output some more useful info into the post-mortem data | Megan Wachs | 1 | -0/+5 | |
| 2018-04-30 | Fix formatting to make pylint happy. | Tim Newsome | 1 | -5/+6 | |
| 2018-04-27 | debug: need to clear satp before changing privdebug-clear-satp | Megan Wachs | 1 | -0/+7 | |
| ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness. | |||||
| 2018-04-27 | Merge pull request #125 from riscv/debug-delete-sim | Megan Wachs | 1 | -17/+0 | |
| Delete E300Sim.py | |||||
| 2018-04-27 | debug: add missing align directive on trap_entrytrap_entry_align-1 | Megan Wachs | 1 | -0/+1 | |
| 2018-04-24 | Fix race when making logs directory | Tim Newsome | 1 | -1/+5 | |
| 2018-04-19 | Delete E300Sim.pydebug-delete-sim | Megan Wachs | 1 | -17/+0 | |
| This file is wrong (the .cfg file isn't right) and not used by anything. | |||||
| 2018-04-09 | Compute gdb command timeout based on ops estimate | Tim Newsome | 2 | -14/+18 | |
| The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122. | |||||
| 2018-04-02 | Use `gdb_report_register_access_error enable` | Tim Newsome | 4 | -0/+6 | |
| 2018-03-27 | Test debug authentication. | Tim Newsome | 4 | -3/+19 | |
| Also halt instead of reset spike targets, which tests a more complicated code path. | |||||
| 2018-03-23 | Print log filename at the end of the log. | Tim Newsome | 1 | -0/+1 | |
| This makes it much easier to look at a log if you see a failure scrolling by on your terminal. | |||||
| 2018-03-01 | Test debugging with/without a program buffer | Tim Newsome | 5 | -5/+10 | |
| 2018-03-01 | Ensure an error when reading a non-existent CSR. | Tim Newsome | 5 | -0/+29 | |
| 2018-02-09 | Test resuming from a trigger.resume_from_trigger | Tim Newsome | 3 | -10/+9 | |
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index : rocket-tools/riscv-tests.git | |
| Unnamed repository; edit this file 'description' to name the repository. | root |
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