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2018-02-27Test debug authentication.debug_authTim Newsome3-3/+18
Also halt instead of reset spike targets, which tests a more complicated code path.
2018-02-07Link scripts shouldn't be executable.Tim Newsome1-0/+0
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
I need this for CompareSections to pass when I instrument spike to be really slow.
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
The Gdb class now can handle connecting to more than one gdb. It enumerates the harts across all connections, and when asked to select a hart, it transparently sends future gdb commands to the correct instance. Multicore tests still have to be aware of some differences. The main one is that when executing 'c' in RTOS mode, all harts resume, while in multi-gdb mode only the current one resumes. Additionally, gdb doesn't set breakpoints until 'c' is issued, so the hart where breakpoints are set needs to be resumed before other harts might see them.
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
Some boards have jumpers that control the reset vector, and forcing them one way or another is more annoying than dealing with it in software.
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
On overloaded systems, when executing compare-sections, otherwise gdb might hit a timeout and the compare-sections code doesn't deal with it. (You get an error message complaining that 130 is not a valid hex digit.)
2017-08-28Make pylint happy.Tim Newsome3-3/+3
2017-08-28WIP multicore testing.Tim Newsome4-0/+8
2017-08-28Make the debug tests aware of multicore.Tim Newsome11-38/+63
Targets now contain an array of harts. When running a regular test, one hart is selected to run the test on while the remaining harts are parked in a safe infinite loop. There's currently only one test that tests multicore behavior, but there could be more. The infrastructure should be able to support heterogeneous multicore, but I don't have a target like that to test with.
2017-08-10Give these sim targets a chance of passing.Tim Newsome2-3/+7
Also make sure vsim.log makes it into the generated log file.
2017-06-26Move target definition into individual files.Tim Newsome21-148/+74
Instead of defining each target in targets.py, now each target gets its own .py file. This means people can easily keep their own target files around that they may not want to put into the main test source. As part of that, I removed the freedom-u500-sim target since I assume it's only used internally at SiFive. Added a few cleanups as well: * Update README examples, mostly --sim_cmd instead of --cmd. * Allow defining misa in a target, to skip running of ExamineTarget. * Rename target.target() to target.create(), which is less confusing. * Default --sim_cmd to `spike` * Got rid of `use_fpu`, instead looking at F or D in $misa.
2017-06-15Test 64-bit addressing.Tim Newsome4-0/+53
The spike64 target now links all test programs at 0x7fff_ffff_ffff_0000. Also a minor change to log file naming so that 'make all' works again. I'll fix this better later.
2017-06-09Add final echo to E300/U500 OpenOCD scriptsTim Newsome2-0/+2
2017-06-09Make HiFive1 testing (mostly) work againTim Newsome2-2/+5
Currently failing: DebugChangeString DebugFunctionCall InstantHaltTest
2017-05-16Link the infinate loop at 0x10000000Palmer Dabbelt1-1/+1
Spike appears to have a problem geterating DTS at 0x80000000.
2017-05-16debug: Update OpenOCD configs.Megan Wachs2-5/+4
2017-05-15Don't use the RTOS, and do "reset halt"Palmer Dabbelt1-3/+4
This is the most reliable way to run the tests for now.
2017-04-18debug: Don't halt out of reset. It's unrealistic. Use a program which loops ↵Megan Wachs1-1/+2
(actually it just gets an exception anyway).
2017-04-18debug: Use RTOS OpenOCD for Spike for now.Megan Wachs1-1/+1
2017-04-17Merge remote-tracking branch 'origin/newprogram' into debug-0.13Megan Wachs5-7/+10
2017-04-17Merge remote-tracking branch 'origin/priv-1.10' into HEADMegan Wachs5-5/+5
2017-04-14debug: checkpoint of trying to get simulation tests workingMegan Wachs5-5/+7
2017-04-14debug: working with newprogram branchMegan Wachs2-3/+4
2017-03-29Change the global pointer symbol to __global_pointer$Palmer Dabbelt5-5/+5
This changed a while ago in binutils.
2017-03-03Resurrect spike debug supportPalmer Dabbelt1-0/+17
2017-02-17Add HiFive1 target.Tim Newsome2-0/+57
2016-10-18Pull port number from VCS output and pass to OpenOCD.Richard Xia2-0/+2
2016-10-03Add test for memory read from invalid address.Tim Newsome1-0/+2
2016-08-11Add FreedomU500 & incorporate feedbackMegan Wachs5-18/+47
2016-08-08Add U500 TargetMegan Wachs2-0/+53
2016-08-08Added FreedomE300 Simulator targetMegan Wachs2-0/+53
2016-07-27Rename m2gl_m2s to freedom-e300.Tim Newsome2-0/+0
It's possible to flash the Freedom E300 onto different FPGA boards, and then debug them in the exact same way.
2016-07-19I think I've finally got malloc working right.Tim Newsome2-4/+7
Now gdb can call functions and change strings.
2016-07-18Increase TCK speed.Tim Newsome1-1/+1
2016-07-18Bump up speed.Tim Newsome1-1/+1
2016-07-18Update IDCODE.Tim Newsome1-1/+1
2016-07-18Add simple register tests.Tim Newsome1-1/+1
Make the RegsTest case a bit more comprehensible.
2016-07-18Add block test.Tim Newsome2-5/+4
2016-07-18All tests pass with spike now.Tim Newsome2-262/+0
I did comment out a couple.
2016-07-18Made some progress towards working with spike.Tim Newsome2-0/+166
I'm writing all the tests so they should just work on real hardware, too.
2016-07-18WIP on debug testing.Tim Newsome3-0/+183
./gdbserver.py --m2gl_m2s --openocd "$HOME/SiFive/openocd/src/openocd -s $HOME/SiFive/openocd/tcl" -- RegsTest.test_write_gprs doesn't fail in a completely crazy way.
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