Age | Commit message (Collapse) | Author | Files | Lines |
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* Parse inf/nan floats.
* Enable mstatus.fs in SimpleF18Test
Also accept "unable to fetch" message when FPRs aren't supported.
* Add config files for HiFive Unleashed.
* Add configs to flash HiFive Unleashed.
All tests pass.
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Tweak debug tests to run out of flash.
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This file is wrong (the .cfg file isn't right) and not used by anything.
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Targets now contain an array of harts. When running a regular test, one
hart is selected to run the test on while the remaining harts are parked
in a safe infinite loop.
There's currently only one test that tests multicore behavior, but there
could be more.
The infrastructure should be able to support heterogeneous multicore,
but I don't have a target like that to test with.
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Also make sure vsim.log makes it into the generated log file.
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Instead of defining each target in targets.py, now each target gets its
own .py file. This means people can easily keep their own target files
around that they may not want to put into the main test source. As part
of that, I removed the freedom-u500-sim target since I assume it's only
used internally at SiFive.
Added a few cleanups as well:
* Update README examples, mostly --sim_cmd instead of --cmd.
* Allow defining misa in a target, to skip running of ExamineTarget.
* Rename target.target() to target.create(), which is less confusing.
* Default --sim_cmd to `spike`
* Got rid of `use_fpu`, instead looking at F or D in $misa.
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