rocket-tools/riscv-tests.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2018-11-14	Merge pull request #165 from riscv/flash	Tim Newsome	2	-0/+59
2018-11-14	Cleanup and renamed test flag to invalid_memory_returns_zero	cgsfv	2	-2/+2
2018-11-13	Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fix	cgsfv	2	-2/+4
2018-10-31	Add HiFive1-flash target configuration.	Tim Newsome	2	-0/+59
2018-09-13	Assert if HiFive1 program is too large.	Tim Newsome	1	-0/+2
2018-04-19	Delete E300Sim.pydebug-delete-sim	Megan Wachs	1	-17/+0
2018-04-02	Use `gdb_report_register_access_error enable`	Tim Newsome	1	-0/+3
2018-03-01	Ensure an error when reading a non-existent CSR.	Tim Newsome	1	-0/+4
2018-02-07	Link scripts shouldn't be executable.	Tim Newsome	1	-0/+0
2017-08-28	Make pylint happy.	Tim Newsome	1	-1/+1
2017-08-28	WIP multicore testing.	Tim Newsome	2	-0/+4
2017-08-28	Make the debug tests aware of multicore.	Tim Newsome	5	-13/+28
2017-08-10	Give these sim targets a chance of passing.	Tim Newsome	2	-3/+7
2017-06-26	Move target definition into individual files.	Tim Newsome	9	-0/+158