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path: root/debug/targets/RISC-V
AgeCommit message (Expand)AuthorFilesLines
2019-04-08Test lack of abstract CSR access. (#187)Tim Newsome6-6/+9
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome4-5/+11
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome3-0/+57
2018-12-31Add testing of run-test/idle cases.Tim Newsome6-6/+7
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome9-0/+9
2018-04-02Use `gdb_report_register_access_error enable`Tim Newsome3-0/+3
2018-03-27Test debug authentication.Tim Newsome3-3/+18
2018-03-01Test debugging with/without a program bufferTim Newsome3-3/+3
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome3-0/+12
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome4-4/+6
2017-10-24Increase dual-core RV64 timeouts.Tim Newsome2-2/+2
2017-09-29Fix tests to work in multi-gdb mode.Tim Newsome9-4/+48
2017-09-21Add coverage for single-core non-rtos OpenOCD.Tim Newsome4-3/+19
2017-09-19Allow multiple reset vectors.Tim Newsome2-2/+2
2017-09-01Use 32-bit link script for 32-bit target.Tim Newsome1-1/+1
2017-08-28This file isn't ready yet.Tim Newsome1-11/+0
2017-08-28Increase remotetimeout for spike targets.Tim Newsome5-0/+15
2017-08-28Make pylint happy.Tim Newsome2-2/+2
2017-08-28WIP multicore testing.Tim Newsome2-0/+4
2017-08-28Make the debug tests aware of multicore.Tim Newsome6-25/+35
2017-06-26Move target definition into individual files.Tim Newsome6-0/+132