aboutsummaryrefslogtreecommitdiff
path: root/debug/gdbserver.py
AgeCommit message (Collapse)AuthorFilesLines
2019-11-19Move to Python 3.python3Tim Newsome1-34/+36
The impetus for this was mostly that after my Ubuntu upgrade, pylint suddenly starting to apply python3 rules, and I suppose it's time to adopt python 3 now that it's been released for more than a decade.
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome1-2/+4
* Parse inf/nan floats. * Enable mstatus.fs in SimpleF18Test Also accept "unable to fetch" message when FPRs aren't supported. * Add config files for HiFive Unleashed. * Add configs to flash HiFive Unleashed. All tests pass.
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome1-8/+7
* Let the debugger enable mstatus.F if necessary. * Ignore (some) gdb debug output. * Increase timeout. * Make newer version of pylint happy.
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome1-1/+4
2019-06-14Work better with mainline gdb (#192)Tim Newsome1-8/+8
* Parse floats the way mainline gdb prints them. For 64-bit floats, it shows both float and double results. Now more tests pass using mainline gdb. * Disable ANSI when talking to gdb. Helps more tests pass with mainline gdb. * Parse {float=...,double=...} in "info registers" Makes tests work better with mainline gdb.
2019-04-04Test simultaneous resume using hasel. (#186)Tim Newsome1-8/+13
Passes on spike and Arty. Won't merge until https://github.com/riscv/riscv-openocd/pull/364 merges.
2019-03-11Add SmpSimultaneousRunHalt test. (#181)Tim Newsome1-0/+49
This test confirms that in SMP configurations OpenOCD halts the harts near-simulatenously. (It'll also check for resume, but that's not implemented yet so commented out for now.)
2019-02-14Test `-rtos hwthread` (#178)Tim Newsome1-10/+12
* WIP * Use hwthread everywhere. * Test `-rtos hwthread`. Also tweak timeouts a bit so that we don't have ridiculous timeouts for simple operations. * Tweak timeouts so tests pass on a loaded system.
2019-01-07Fail on unsupported SREC type.Tim Newsome1-0/+2
2018-12-31Fix MemTestBlockTim Newsome1-20/+41
This test used to false pass on 64-bit targets because gdb doesn't like using Intel hex files on 64-bit targets.
2018-12-03Reduce download size a bit.Tim Newsome1-4/+8
Increase some timeouts in case memory access is slow.
2018-11-30Use more than 1KB for download test.Tim Newsome1-1/+1
This is a pretty old bug. I limited the size to 256KB because against spike my machine gets about 8KB/s, and I don't want to wait forever for `make` to pass.
2018-11-16Make pylint happy.Tim Newsome1-3/+6
2018-11-14Merge pull request #165 from riscv/flashTim Newsome1-13/+33
Tweak debug tests to run out of flash.
2018-11-14Cleanup and renamed test flag to invalid_memory_returns_zerocgsfv1-2/+2
2018-11-13Added MemTestBlockReadInvalid verifying the corresponding OpenOCD fixcgsfv1-0/+52
2018-10-31Fix remaining tests to work from flash:Tim Newsome1-4/+12
TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint.
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome1-3/+12
Only TriggerDmode still fails.
2018-10-29Tweak debug tests to run out of flash.Tim Newsome1-6/+9
Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant.
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
Gdb and OpenOCD were fixed so we don't have to accept broken behavior anymore.
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome1-5/+8
Also tiny cleanups, making pylint happy.
2018-10-03Added tests for hw and sw watchpointscgsfv1-0/+56
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
Reset address translation/perms before PrivChange
2018-08-31Fix CustomRegisterTest.Tim Newsome1-1/+2
gdb in riscv-tools doesn't automatically create a "custom" group like mainline gdb does.
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome1-0/+30
Only works against spike, where I've implemented some custom debug registers to test against.
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
We already did this for PrivTest. Hopefully solves #155, but I haven't been able to reproduce it.
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful.
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
@timsifive we are debugging intermittent failures.
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome1-2/+3
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
Add debug test, which checks that openocd correctly switch active thread on any hart halt.
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification
2018-08-22Add debug test, which checks that openocd correctly switch active thread on ↵Dmitry Ryzhov1-0/+28
any hart halt.
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use.
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome1-19/+37
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so.
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs1-17/+4
2018-05-14Make DownloadTest properly park other harts.Tim Newsome1-1/+2
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
2018-04-09Compute gdb command timeout based on ops estimateTim Newsome1-1/+1
The caller of gdb.command() should estimate how much work gdb needs to do, and testlib then scales this up proportional to the general gdb timeout we configured. This hopefully allows us to configure a tighter timeout, so we don't have to have a multi-hour timeout just for something that takes long like `load` on a really slow simulator. Hopefully this addresses #122.
2018-03-01Ensure an error when reading a non-existent CSR.Tim Newsome1-0/+13
2018-02-09Test resuming from a trigger.resume_from_triggerTim Newsome1-0/+5
2018-01-08Deal with gdb reporting pmpcfg0 not existing.Tim Newsome1-3/+7
It's an optional register.
2018-01-05Add test for multicore failureTim Newsome1-0/+28
Specifically, make sure that after resuming all cores, and halting core 0, that OpenOCD's poll() doesn't mess up the currently selected hart to the point where memory accesses intended for core 0 go to core 1.
2017-12-27Test FPRs that aren't XLEN in size.Tim Newsome1-0/+6
Cover all combinations of 32,64 bit XLEN with F and FD extensions. Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
generated by cgit v1.1 at 2026-02-27 03:36:57 +0000