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The impetus for this was mostly that after my Ubuntu upgrade, pylint
suddenly starting to apply python3 rules, and I suppose it's time to
adopt python 3 now that it's been released for more than a decade.
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* Parse inf/nan floats.
* Enable mstatus.fs in SimpleF18Test
Also accept "unable to fetch" message when FPRs aren't supported.
* Add config files for HiFive Unleashed.
* Add configs to flash HiFive Unleashed.
All tests pass.
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* Let the debugger enable mstatus.F if necessary.
* Ignore (some) gdb debug output.
* Increase timeout.
* Make newer version of pylint happy.
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* Parse floats the way mainline gdb prints them.
For 64-bit floats, it shows both float and double results. Now more
tests pass using mainline gdb.
* Disable ANSI when talking to gdb.
Helps more tests pass with mainline gdb.
* Parse {float=...,double=...} in "info registers"
Makes tests work better with mainline gdb.
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Passes on spike and Arty. Won't merge until
https://github.com/riscv/riscv-openocd/pull/364 merges.
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This test confirms that in SMP configurations OpenOCD halts the harts
near-simulatenously. (It'll also check for resume, but that's not
implemented yet so commented out for now.)
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* WIP
* Use hwthread everywhere.
* Test `-rtos hwthread`.
Also tweak timeouts a bit so that we don't have ridiculous timeouts for
simple operations.
* Tweak timeouts so tests pass on a loaded system.
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This test used to false pass on 64-bit targets because gdb doesn't like
using Intel hex files on 64-bit targets.
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Increase some timeouts in case memory access is slow.
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This is a pretty old bug. I limited the size to 256KB because against
spike my machine gets about 8KB/s, and I don't want to wait forever for
`make` to pass.
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Tweak debug tests to run out of flash.
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TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint.
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Only TriggerDmode still fails.
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Not all tests pass when run out of flash yet, but it's getting a lot
closer. The ones still failing on HiFive1-flash are: DebugSymbols,
Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and
TriggerStoreAddressInstant.
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Gdb and OpenOCD were fixed so we don't have to accept broken behavior
anymore.
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Also tiny cleanups, making pylint happy.
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Reset address translation/perms before PrivChange
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gdb in riscv-tools doesn't automatically create a "custom" group like
mainline gdb does.
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Only works against spike, where I've implemented some custom debug
registers to test against.
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We already did this for PrivTest.
Hopefully solves #155, but I haven't been able to reproduce it.
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Now that OpenOCD can tell gdb exactly which watchpoint was hit, this
test exposes another problem:
https://github.com/riscv/riscv-openocd/issues/295
For now neuter the test so the testsuite can still be useful.
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@timsifive we are debugging intermittent failures.
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Add debug test, which checks that openocd correctly switch active thread on any hart halt.
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It's failing (intermittently?). See eg.
https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification
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any hart halt.
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Newer gdb requires more debug info in order to "watch data" in this
test. I'm not sure how to make that debug info happen, so instead we
tell it the address to use.
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The test actually wasn't checking interrupt counts at all. Fixing it
required some other changes:
Make sure all harts get to run
Add some retries, since on a loaded machine against spike both harts
might not get to run, even if you give spike a generous amount of time
to do so.
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ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
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The caller of gdb.command() should estimate how much work gdb needs to
do, and testlib then scales this up proportional to the general gdb
timeout we configured. This hopefully allows us to configure a tighter
timeout, so we don't have to have a multi-hour timeout just for
something that takes long like `load` on a really slow simulator.
Hopefully this addresses #122.
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It's an optional register.
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Specifically, make sure that after resuming all cores, and halting core
0, that OpenOCD's poll() doesn't mess up the currently selected hart to
the point where memory accesses intended for core 0 go to core 1.
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Cover all combinations of 32,64 bit XLEN with F and FD extensions.
Finishes Issue https://github.com/riscv/riscv-openocd/issues/110
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