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2020-03-21Fix regression introduced by 24d7d6b68c5581c36cbdef354b1882a7a8dd52c5Andrew Waterman1-7/+7
2020-03-21Move self-modifying 'fence.i' ops to .data memory section (#269)WRansohoff1-6/+14
2020-03-19Fix comments error in fmin.S (#267)Mohanson2-4/+4
2020-03-18Spike changed --varch syntax (#257)Tim Newsome1-2/+2
2020-03-18Specify misa for HiFive Unleashed. (#259)Tim Newsome1-0/+2
2020-03-18Have both rs=rd and rs!=rd cases in csr.S (#263)Takahiro1-12/+15
2020-03-18Fix shamt.S header (#264)Takahiro1-2/+2
2020-03-16Add a test case rs = rd to jalr.S (#258)Takahiro1-0/+16
2020-03-11Add comment explaining convoluted rv64mi-p-scall behaviorAndrew Waterman1-0/+6
2020-03-11Revert "scall: make the intention of the test in machine mode more clear (#246)"Andrew Waterman1-6/+1
2020-03-11Setup a multilevel page table to avoid misaligned superpages caused by variab...Cedric Orban1-0/+4
2020-03-06Don't assume reset state of mscratch (#254)Paul Donahue2-13/+13
2020-03-05bump env (#253)Han-Kuan Chen1-12/+12
2020-03-05Bump riscv-test-env (#252)Andrew Waterman1-5/+17
2020-03-05Clean up gdb parsing code. (#247)Tim Newsome1-42/+32
2020-03-05Add a simple mechanism to skip tests on targets. (#251)Tim Newsome2-1/+9
2020-03-02enable rv32e compatability by replacing reg x29 with reg x7 (#250)Cedric Orban1-12/+12
2020-02-27bump envAndrew Waterman1-10/+5
2020-02-21scall: make the intention of the test in machine mode more clear (#246)Nils Asmussen1-1/+6
2020-02-20Fix rv64mi-p-csr on systems with FPUsAndrew Waterman1-2/+3
2020-02-14Add tests for vector register access (#244)Tim Newsome5-34/+137
2020-02-11Generate very different values on different harts. (#238)Tim Newsome2-4/+5
2020-02-11Run OpenOCD output through spike-dasm. (#239)Tim Newsome1-3/+9
2020-02-11Look for \bmain\b instead of ' main '. (#237)Tim Newsome1-2/+2
2020-02-08Solves https://github.com/riscv/riscv-tests/issues/241 : Each mhartid has the...Sho Nakatani1-2/+2
2020-01-31Added CSR test cases on whether writing 0 to CSR works, as that might get ove...Torbjørn Viem Ness1-0/+2
2020-01-15Force DMI busy in all tests. (#235)Tim Newsome2-15/+44
2020-01-09Smoke test virtual address translation support. (#233)Tim Newsome6-13/+231
2019-12-28benchmarks: Disassemble .text.init section (#230)Albert Ou1-1/+1
2019-12-24submodule: bump env version (#229)Chih-Min Chao1-5/+10
2019-12-18Hardcode misa values for all spike targets. (#227)Tim Newsome9-7/+27
2019-12-18Tell people where to get software. (#226)Tim Newsome1-3/+9
2019-12-10benchmarks: Simplify TLS initialisation (#224)James Clarke3-19/+5
2019-12-10Improve parallellism in debug test Makefile (#223)Tim Newsome2-15/+28
2019-12-02Use a small binary to set up HiFive Unleashed. (#221)Tim Newsome3-10/+10
2019-11-22Move to Python 3. (#218)Tim Newsome4-75/+78
2019-11-04Remove cruft from icache-alias testAndrew Waterman1-35/+0
2019-11-04Add rv64si-p-icache-aliasAndrew Waterman2-0/+177
2019-10-15Add support to run all tests against HiFive Unleashed. (#212)Tim Newsome7-3/+191
2019-10-09Remove ocd_ prefix. (#210)Tim Newsome4-4/+4
2019-09-24Redo the debug README. (#205)Tim Newsome1-26/+19
2019-09-24Look for binaries in $PATH. (#208)Tim Newsome1-7/+4
2019-09-19Small debug test improvements. (#204)Tim Newsome0-0/+0
2019-08-02Miscellaneous minor test improvements (#199)Tim Newsome4-19/+20
2019-07-29Support RV32E. Fixed #198 (#200)Leway Colin3-42/+42
2019-07-15Make tests work with RV32E targets. (#196)Tim Newsome5-27/+45
2019-07-15Use work area in spike-1 to cover CRC algorithm. (#195)Tim Newsome2-1/+6
2019-07-01pmp: first set the address, then cfg (#194)Pentin Alexander Sergeevich1-1/+1
2019-06-14Work better with mainline gdb (#192)Tim Newsome2-23/+46
2019-05-16Cover with/without halt groups. (#191)Tim Newsome5-12/+20
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