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2018-10-31Fix remaining tests to work from flash:Tim Newsome2-6/+17
TriggerDmode, ProgramHwWatchpoint, ProgramSwWatchpoint.
2018-10-29Almost all tests pass with HiFive1-flashTim Newsome2-4/+13
Only TriggerDmode still fails.
2018-10-29Tweak debug tests to run out of flash.Tim Newsome4-8/+17
Not all tests pass when run out of flash yet, but it's getting a lot closer. The ones still failing on HiFive1-flash are: DebugSymbols, Hwbp2, InstantHaltTest, TriggerDmode, TriggerLoadAddressInstant, and TriggerStoreAddressInstant.
2018-10-24Merge branch 'TriggerLoadAddressInstant'Tim Newsome1-12/+1
2018-10-24Re-enable TriggerStoreAddressInstantTim Newsome1-12/+1
Gdb and OpenOCD were fixed so we don't have to accept broken behavior anymore.
2018-10-05Make HwWatchpoint test fail on incorrect result.hw_watchpointTim Newsome3-7/+10
Also tiny cleanups, making pylint happy.
2018-10-03Added tests for hw and sw watchpointscgsfv3-0/+88
2018-09-23bump envAndrew Waterman1-5/+5
2018-09-13Assert if HiFive1 program is too large.Tim Newsome1-0/+2
2018-09-13Put debug test stack in data instead of textTim Newsome1-0/+1
2018-09-08Merge branch 'tommythorn-master'Andrew Waterman6-0/+42
2018-09-08RV64 s{ll,ra,rl}w tests with non-canonical valuesTommy Thorn6-0/+42
2018-09-06Revert "breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) ↵Andrew Waterman1-1/+1
(#159)" This reverts commit 901a2694d5384e4ef9af8e4fb0c9a07eb24d0028, under the advisement of @tommythorn in #158.
2018-09-06breakpoint.S: Don't assume trigger is hardwired to breakpoint (#158) (#159)Tommy Thorn1-1/+1
2018-09-03Merge pull request #156 from riscv/PrivChangeTim Newsome1-27/+26
Reset address translation/perms before PrivChange
2018-08-31Fix CustomRegisterTest.Tim Newsome2-5/+6
gdb in riscv-tools doesn't automatically create a "custom" group like mainline gdb does.
2018-08-29Add test case for `riscv expose_custom`.Tim Newsome12-0/+55
Only works against spike, where I've implemented some custom debug registers to test against.
2018-08-28Reset address translation/perms before PrivChangeTim Newsome1-27/+26
We already did this for PrivTest. Hopefully solves #155, but I haven't been able to reproduce it.
2018-08-27Neuter TriggerStoreAddressInstantTim Newsome1-1/+13
Now that OpenOCD can tell gdb exactly which watchpoint was hit, this test exposes another problem: https://github.com/riscv/riscv-openocd/issues/295 For now neuter the test so the testsuite can still be useful.
2018-08-27Make pylint happy.Tim Newsome1-1/+2
2018-08-25Temporarily disabling PrivChange testAndrew Waterman1-22/+23
@timsifive we are debugging intermittent failures.
2018-08-23Make pylint happy with change d1d2d953b5016b465.Tim Newsome2-3/+4
2018-08-23Get all of the log into the final log fileTim Newsome1-6/+20
This allows me to see the final valgrind output on OpenOCD, so I can watch for memory leaks when using --server_cmd "valgrind --leak-check=full openocd".
2018-08-23Merge pull request #153 from dmitryryzhov/rtos-switch-active-threadTim Newsome1-0/+28
Add debug test, which checks that openocd correctly switch active thread on any hart halt.
2018-08-22Merge branch 'master' of https://github.com/riscv/riscv-testsTim Newsome1-2/+2
2018-08-22Disable MulticoreRunHaltStepiTestTim Newsome1-52/+52
It's failing (intermittently?). See eg. https://travis-ci.org/riscv/riscv-tools/builds/418928412?utm_source=github_status&utm_medium=notification
2018-08-22Add debug test, which checks that openocd correctly switch active thread on ↵Dmitry Ryzhov1-0/+28
any hart halt.
2018-08-21Changing the register mstatus is read into (#152)Srivatsa Yogendra1-2/+2
The mstatus reading overwrites the expected user mode cause value.
2018-08-20Revert "Fix to solve the failing tests shamt, csr and scall (#151)"Andrew Waterman2-52/+5
This reverts commit 31a91823b7c7becacd06c9c32e44180eea5e4fe7. These changes should be made to the test environment, not the tests themselves.
2018-08-17Fix to solve the failing tests shamt, csr and scall (#151)Srivatsa Yogendra2-5/+52
* making mtvec_handler global * Adding the pmp configuration inst The PMP config instructions are added as the test jumps to user mode * Adding pmp config inst Adding pmp config instructions as the test jumps to user mode * changing to PMP macros * changing to PMP Macros * moving the #endif after pmp initialization * Removing the unwanted label
2018-08-17making mtvec_handler global (#150)Srivatsa Yogendra1-0/+1
2018-08-13Add jump/hbreak test.Tim Newsome1-0/+23
2018-07-09Check that SC yields the load reservationAndrew Waterman1-0/+9
https://github.com/riscv/riscv-isa-manual/commit/03a5e722fc0fe7b94dd0a49f550ff7b41a63f612
2018-07-03rwatch/watch on explicit addressTim Newsome1-2/+4
Newer gdb requires more debug info in order to "watch data" in this test. I'm not sure how to make that debug info happen, so instead we tell it the address to use.
2018-06-18Add reproduce line to the end of debug test logsTim Newsome1-0/+2
2018-05-21Merge pull request #141 from riscv/mrhstestTim Newsome2-23/+46
Fix MulticoreRunHaltStepiTest
2018-05-18Fix MulticoreRunHaltStepiTestTim Newsome2-23/+46
The test actually wasn't checking interrupt counts at all. Fixing it required some other changes: Make sure all harts get to run Add some retries, since on a loaded machine against spike both harts might not get to run, even if you give spike a generous amount of time to do so.
2018-05-15Merge pull request #139 from riscv/debug-tests-more-singleMegan Wachs2-10/+19
Mark more Debug tests as "Single Hart"
2018-05-14Merge remote-tracking branch 'origin/downloadtest' into debug-tests-more-singleMegan Wachs2-21/+11
2018-05-14Make DownloadTest properly park other harts.Tim Newsome2-5/+9
2018-05-14debug: remove some unintentionally added newlinesMegan Wachs1-2/+0
2018-05-14debug: Fixing the non-RTOS behavior for DownloadTestMegan Wachs1-7/+16
2018-05-11debug: mark more tests as single-hart testsMegan Wachs1-6/+13
2018-05-11debug: output some more useful info into the post-mortem dataMegan Wachs1-0/+5
2018-04-30[rv64ua/lrsc] Initialize memory read out. (#135)Christopher Celio1-1/+3
* [rv64ua/lrsc] Initialize memory read out. Even though the load contents are discarded, this un-initialized memory value can lead to a divergence for co-simulation between two different RISC-V designs. * [rv64ua/lrsc] Use .skip instead of .align.
2018-04-30Fix formatting to make pylint happy.Tim Newsome1-5/+6
2018-04-28Merge pull request #132 from riscv/debug-clear-satpMegan Wachs1-0/+7
debug: need to clear satp before changing priv
2018-04-27debug: need to clear satp before changing privdebug-clear-satpMegan Wachs1-0/+7
ISA Manual does not require this register to be reset, and attempting to execute code with VM on when VM hasn't been set up is going to just lead to sadness.
2018-04-27Merge pull request #125 from riscv/debug-delete-simMegan Wachs1-17/+0
Delete E300Sim.py
2018-04-27Merge pull request #130 from riscv/trap_entry_align-1Megan Wachs1-0/+1
debug: add missing align directive on trap_entry
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